Andreas Olofsson 0964fae184 Changing to sync fifo ...

- The response time for async fifo was not fast enough due to synchronization, was causing problems when connecting memory/reg directly to output.
- Was found in testbench, but is generally applicable.
- Also simplifying/refactoring names

2016-01-19 13:25:19 -05:00

..

dv

Adding stub files for axi master and slave

2015-11-18 23:23:31 -05:00

hdl

Changing to sync fifo

2016-01-19 13:25:19 -05:00