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40 lines
978 B
Verilog
40 lines
978 B
Verilog
module IBUFE3 #(
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`ifdef XIL_TIMING
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parameter LOC = "UNPLACED",
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`endif
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parameter IBUF_LOW_PWR = "TRUE",
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parameter IOSTANDARD = "DEFAULT",
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parameter integer SIM_INPUT_BUFFER_OFFSET = 0,
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parameter USE_IBUFDISABLE = "FALSE"
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)(
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output O,
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input I,
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input IBUFDISABLE,
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input [3:0] OSC,
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input OSC_EN,
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input VREF
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);
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// define constants
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localparam MODULE_NAME = "IBUFE3";
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localparam in_delay = 0;
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localparam out_delay = 0;
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localparam inclk_delay = 0;
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localparam outclk_delay = 0;
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// Parameter encodings and registers
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localparam IBUF_LOW_PWR_FALSE = 1;
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localparam IBUF_LOW_PWR_TRUE = 0;
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localparam USE_IBUFDISABLE_FALSE = 0;
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localparam USE_IBUFDISABLE_TRUE = 1;
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// include dynamic registers - XILINX test only
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reg trig_attr = 1'b0;
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localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
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localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
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localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;
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endmodule
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