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30 lines
427 B
Verilog
30 lines
427 B
Verilog
module OBUF (/*AUTOARG*/
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// Outputs
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O,
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// Inputs
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I
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);
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parameter CAPACITANCE = "DONT_CARE";
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parameter integer DRIVE = 12;
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parameter IOSTANDARD = "DEFAULT";
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`ifdef XIL_TIMING
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parameter LOC = " UNPLACED";
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`endif
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parameter SLEW = "SLOW";
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output O;
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input I;
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wire GTS = 1'b0; //Note, uses globals, ugly!
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bufif0 B1 (O, I, GTS);
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endmodule
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