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https://github.com/aolofsson/oh.git
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1508afa2ea
Not convinced that it's good to do this in text... (but it's always good to know what's underneath the hood) Vivado IP generates wrappers after all
879 lines
30 KiB
Verilog
879 lines
30 KiB
Verilog
//Version v5_5
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module processing_system7 (
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#(
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parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
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parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
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parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
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parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
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parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
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parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
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parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
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parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
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parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
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parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
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parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
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parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
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parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
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parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
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parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
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parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
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parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
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parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
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parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
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parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
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parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
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parameter integer C_NUM_F2P_INTR_INPUTS = 1,
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parameter C_FCLK_CLK0_BUF = "TRUE",
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parameter C_FCLK_CLK1_BUF = "TRUE",
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parameter C_FCLK_CLK2_BUF = "TRUE",
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parameter C_FCLK_CLK3_BUF = "TRUE",
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parameter integer C_EMIO_GPIO_WIDTH = 64,
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parameter integer C_INCLUDE_TRACE_BUFFER = 0,
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parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
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parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
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parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
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parameter integer C_TRACE_PIPELINE_WIDTH = 8,
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parameter C_PS7_SI_REV = "PRODUCTION",
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parameter integer C_EN_EMIO_ENET0 = 0,
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parameter integer C_EN_EMIO_ENET1 = 0,
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parameter integer C_EN_EMIO_TRACE = 0,
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parameter integer C_DQ_WIDTH = 32,
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parameter integer C_DQS_WIDTH = 4,
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parameter integer C_DM_WIDTH = 4,
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parameter integer C_MIO_PRIMITIVE = 54,
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parameter C_PACKAGE_NAME = "clg484",
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parameter C_IRQ_F2P_MODE = "DIRECT",
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parameter C_TRACE_INTERNAL_WIDTH = 32,
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parameter integer C_EN_EMIO_PJTAG = 0
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)
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//FMIO CAN0
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output CAN0_PHY_TX,
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input CAN0_PHY_RX,
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//FMIO CAN1
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output CAN1_PHY_TX,
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input CAN1_PHY_RX,
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//FMIO ENET0
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output reg ENET0_GMII_TX_EN,
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output reg ENET0_GMII_TX_ER,
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output ENET0_MDIO_MDC,
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output ENET0_MDIO_O,
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output ENET0_MDIO_T,
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output ENET0_PTP_DELAY_REQ_RX,
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output ENET0_PTP_DELAY_REQ_TX,
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output ENET0_PTP_PDELAY_REQ_RX,
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output ENET0_PTP_PDELAY_REQ_TX,
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output ENET0_PTP_PDELAY_RESP_RX,
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output ENET0_PTP_PDELAY_RESP_TX,
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output ENET0_PTP_SYNC_FRAME_RX,
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output ENET0_PTP_SYNC_FRAME_TX,
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output ENET0_SOF_RX,
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output ENET0_SOF_TX,
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output reg [7:0] ENET0_GMII_TXD,
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input ENET0_GMII_COL,
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input ENET0_GMII_CRS,
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input ENET0_GMII_RX_CLK,
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input ENET0_GMII_RX_DV,
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input ENET0_GMII_RX_ER,
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input ENET0_GMII_TX_CLK,
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input ENET0_MDIO_I,
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input ENET0_EXT_INTIN,
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input [7:0] ENET0_GMII_RXD,
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//FMIO ENET1
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output reg ENET1_GMII_TX_EN,
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output reg ENET1_GMII_TX_ER,
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output ENET1_MDIO_MDC,
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output ENET1_MDIO_O,
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output ENET1_MDIO_T,
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output ENET1_PTP_DELAY_REQ_RX,
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output ENET1_PTP_DELAY_REQ_TX,
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output ENET1_PTP_PDELAY_REQ_RX,
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output ENET1_PTP_PDELAY_REQ_TX,
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output ENET1_PTP_PDELAY_RESP_RX,
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output ENET1_PTP_PDELAY_RESP_TX,
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output ENET1_PTP_SYNC_FRAME_RX,
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output ENET1_PTP_SYNC_FRAME_TX,
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output ENET1_SOF_RX,
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output ENET1_SOF_TX,
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output reg [7:0] ENET1_GMII_TXD,
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input ENET1_GMII_COL,
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input ENET1_GMII_CRS,
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input ENET1_GMII_RX_CLK,
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input ENET1_GMII_RX_DV,
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input ENET1_GMII_RX_ER,
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input ENET1_GMII_TX_CLK,
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input ENET1_MDIO_I,
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input ENET1_EXT_INTIN,
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input [7:0] ENET1_GMII_RXD,
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//FMIO GPIO
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input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
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output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
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output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
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//FMIO I2C0
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input I2C0_SDA_I,
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output I2C0_SDA_O,
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output I2C0_SDA_T,
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input I2C0_SCL_I,
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output I2C0_SCL_O,
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output I2C0_SCL_T,
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//FMIO I2C1
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input I2C1_SDA_I,
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output I2C1_SDA_O,
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output I2C1_SDA_T,
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input I2C1_SCL_I,
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output I2C1_SCL_O,
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output I2C1_SCL_T,
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//FMIO PJTAG
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input PJTAG_TCK,
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input PJTAG_TMS,
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input PJTAG_TDI,
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output PJTAG_TDO,
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//FMIO SDIO0
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output SDIO0_CLK,
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input SDIO0_CLK_FB,
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output SDIO0_CMD_O,
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input SDIO0_CMD_I,
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output SDIO0_CMD_T,
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input [3:0] SDIO0_DATA_I,
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output [3:0] SDIO0_DATA_O,
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output [3:0] SDIO0_DATA_T,
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output SDIO0_LED,
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input SDIO0_CDN,
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input SDIO0_WP,
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output SDIO0_BUSPOW,
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output [2:0] SDIO0_BUSVOLT,
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//FMIO SDIO1
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output SDIO1_CLK,
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input SDIO1_CLK_FB,
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output SDIO1_CMD_O,
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input SDIO1_CMD_I,
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output SDIO1_CMD_T,
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input [3:0] SDIO1_DATA_I,
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output [3:0] SDIO1_DATA_O,
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output [3:0] SDIO1_DATA_T,
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output SDIO1_LED,
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input SDIO1_CDN,
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input SDIO1_WP,
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output SDIO1_BUSPOW,
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output [2:0] SDIO1_BUSVOLT,
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//FMIO SPI0
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input SPI0_SCLK_I,
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output SPI0_SCLK_O,
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output SPI0_SCLK_T,
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input SPI0_MOSI_I,
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output SPI0_MOSI_O,
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output SPI0_MOSI_T,
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input SPI0_MISO_I,
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output SPI0_MISO_O,
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output SPI0_MISO_T,
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input SPI0_SS_I,
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output SPI0_SS_O,
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output SPI0_SS1_O,
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output SPI0_SS2_O,
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output SPI0_SS_T,
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//FMIO SPI1
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input SPI1_SCLK_I,
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output SPI1_SCLK_O,
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output SPI1_SCLK_T,
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input SPI1_MOSI_I,
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output SPI1_MOSI_O,
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output SPI1_MOSI_T,
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input SPI1_MISO_I,
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output SPI1_MISO_O,
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output SPI1_MISO_T,
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input SPI1_SS_I,
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output SPI1_SS_O,
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output SPI1_SS1_O,
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output SPI1_SS2_O,
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output SPI1_SS_T,
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//FMIO UART0
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output UART0_DTRN,
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output UART0_RTSN,
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output UART0_TX,
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input UART0_CTSN,
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input UART0_DCDN,
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input UART0_DSRN,
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input UART0_RIN,
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input UART0_RX,
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//FMIO UART1
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output UART1_DTRN,
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output UART1_RTSN,
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output UART1_TX,
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input UART1_CTSN,
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input UART1_DCDN,
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input UART1_DSRN,
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input UART1_RIN,
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input UART1_RX,
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//FMIO TTC0
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output TTC0_WAVE0_OUT,
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output TTC0_WAVE1_OUT,
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output TTC0_WAVE2_OUT,
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input TTC0_CLK0_IN,
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input TTC0_CLK1_IN,
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input TTC0_CLK2_IN,
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//FMIO TTC1
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output TTC1_WAVE0_OUT,
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output TTC1_WAVE1_OUT,
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output TTC1_WAVE2_OUT,
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input TTC1_CLK0_IN,
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input TTC1_CLK1_IN,
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input TTC1_CLK2_IN,
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//WDT
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input WDT_CLK_IN,
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output WDT_RST_OUT,
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//FTPORT
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input TRACE_CLK,
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output TRACE_CTL,
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output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
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output reg TRACE_CLK_OUT,
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// USB
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output [1:0] USB0_PORT_INDCTL,
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output USB0_VBUS_PWRSELECT,
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input USB0_VBUS_PWRFAULT,
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output [1:0] USB1_PORT_INDCTL,
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output USB1_VBUS_PWRSELECT,
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input USB1_VBUS_PWRFAULT,
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input SRAM_INTIN,
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//AIO ===================================================
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//M_AXI_GP0
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// -- Output
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output M_AXI_GP0_ARESETN,
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output M_AXI_GP0_ARVALID,
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output M_AXI_GP0_AWVALID,
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output M_AXI_GP0_BREADY,
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output M_AXI_GP0_RREADY,
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output M_AXI_GP0_WLAST,
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output M_AXI_GP0_WVALID,
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output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
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output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
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output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
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output [1:0] M_AXI_GP0_ARBURST,
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output [1:0] M_AXI_GP0_ARLOCK,
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output [2:0] M_AXI_GP0_ARSIZE,
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output [1:0] M_AXI_GP0_AWBURST,
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output [1:0] M_AXI_GP0_AWLOCK,
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output [2:0] M_AXI_GP0_AWSIZE,
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output [2:0] M_AXI_GP0_ARPROT,
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output [2:0] M_AXI_GP0_AWPROT,
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output [31:0] M_AXI_GP0_ARADDR,
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output [31:0] M_AXI_GP0_AWADDR,
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output [31:0] M_AXI_GP0_WDATA,
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output [3:0] M_AXI_GP0_ARCACHE,
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output [3:0] M_AXI_GP0_ARLEN,
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output [3:0] M_AXI_GP0_ARQOS,
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output [3:0] M_AXI_GP0_AWCACHE,
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output [3:0] M_AXI_GP0_AWLEN,
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output [3:0] M_AXI_GP0_AWQOS,
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output [3:0] M_AXI_GP0_WSTRB,
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// -- Input
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input M_AXI_GP0_ACLK,
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input M_AXI_GP0_ARREADY,
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input M_AXI_GP0_AWREADY,
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input M_AXI_GP0_BVALID,
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input M_AXI_GP0_RLAST,
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input M_AXI_GP0_RVALID,
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input M_AXI_GP0_WREADY,
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input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
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input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
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input [1:0] M_AXI_GP0_BRESP,
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input [1:0] M_AXI_GP0_RRESP,
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input [31:0] M_AXI_GP0_RDATA,
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//M_AXI_GP1
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// -- Output
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output M_AXI_GP1_ARESETN,
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output M_AXI_GP1_ARVALID,
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output M_AXI_GP1_AWVALID,
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output M_AXI_GP1_BREADY,
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output M_AXI_GP1_RREADY,
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output M_AXI_GP1_WLAST,
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output M_AXI_GP1_WVALID,
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output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
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output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
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output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
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output [1:0] M_AXI_GP1_ARBURST,
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output [1:0] M_AXI_GP1_ARLOCK,
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output [2:0] M_AXI_GP1_ARSIZE,
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output [1:0] M_AXI_GP1_AWBURST,
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output [1:0] M_AXI_GP1_AWLOCK,
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output [2:0] M_AXI_GP1_AWSIZE,
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output [2:0] M_AXI_GP1_ARPROT,
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output [2:0] M_AXI_GP1_AWPROT,
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output [31:0] M_AXI_GP1_ARADDR,
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output [31:0] M_AXI_GP1_AWADDR,
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output [31:0] M_AXI_GP1_WDATA,
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output [3:0] M_AXI_GP1_ARCACHE,
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output [3:0] M_AXI_GP1_ARLEN,
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output [3:0] M_AXI_GP1_ARQOS,
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output [3:0] M_AXI_GP1_AWCACHE,
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output [3:0] M_AXI_GP1_AWLEN,
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output [3:0] M_AXI_GP1_AWQOS,
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output [3:0] M_AXI_GP1_WSTRB,
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// -- Input
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input M_AXI_GP1_ACLK,
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input M_AXI_GP1_ARREADY,
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input M_AXI_GP1_AWREADY,
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input M_AXI_GP1_BVALID,
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input M_AXI_GP1_RLAST,
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input M_AXI_GP1_RVALID,
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input M_AXI_GP1_WREADY,
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input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
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input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
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input [1:0] M_AXI_GP1_BRESP,
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input [1:0] M_AXI_GP1_RRESP,
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input [31:0] M_AXI_GP1_RDATA,
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// S_AXI_GP0
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// -- Output
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output S_AXI_GP0_ARESETN,
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output S_AXI_GP0_ARREADY,
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output S_AXI_GP0_AWREADY,
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output S_AXI_GP0_BVALID,
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output S_AXI_GP0_RLAST,
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output S_AXI_GP0_RVALID,
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output S_AXI_GP0_WREADY,
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output [1:0] S_AXI_GP0_BRESP,
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output [1:0] S_AXI_GP0_RRESP,
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output [31:0] S_AXI_GP0_RDATA,
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output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
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output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
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// -- Input
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input S_AXI_GP0_ACLK,
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input S_AXI_GP0_ARVALID,
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input S_AXI_GP0_AWVALID,
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input S_AXI_GP0_BREADY,
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input S_AXI_GP0_RREADY,
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input S_AXI_GP0_WLAST,
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input S_AXI_GP0_WVALID,
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input [1:0] S_AXI_GP0_ARBURST,
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input [1:0] S_AXI_GP0_ARLOCK,
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input [2:0] S_AXI_GP0_ARSIZE,
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input [1:0] S_AXI_GP0_AWBURST,
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input [1:0] S_AXI_GP0_AWLOCK,
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input [2:0] S_AXI_GP0_AWSIZE,
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input [2:0] S_AXI_GP0_ARPROT,
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input [2:0] S_AXI_GP0_AWPROT,
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input [31:0] S_AXI_GP0_ARADDR,
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input [31:0] S_AXI_GP0_AWADDR,
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input [31:0] S_AXI_GP0_WDATA,
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input [3:0] S_AXI_GP0_ARCACHE,
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input [3:0] S_AXI_GP0_ARLEN,
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input [3:0] S_AXI_GP0_ARQOS,
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input [3:0] S_AXI_GP0_AWCACHE,
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input [3:0] S_AXI_GP0_AWLEN,
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input [3:0] S_AXI_GP0_AWQOS,
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input [3:0] S_AXI_GP0_WSTRB,
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input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
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input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
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input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
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// S_AXI_GP1
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// -- Output
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output S_AXI_GP1_ARESETN,
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output S_AXI_GP1_ARREADY,
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output S_AXI_GP1_AWREADY,
|
|
output S_AXI_GP1_BVALID,
|
|
output S_AXI_GP1_RLAST,
|
|
output S_AXI_GP1_RVALID,
|
|
output S_AXI_GP1_WREADY,
|
|
output [1:0] S_AXI_GP1_BRESP,
|
|
output [1:0] S_AXI_GP1_RRESP,
|
|
output [31:0] S_AXI_GP1_RDATA,
|
|
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
|
|
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
|
|
|
|
// -- Input
|
|
input S_AXI_GP1_ACLK,
|
|
input S_AXI_GP1_ARVALID,
|
|
input S_AXI_GP1_AWVALID,
|
|
input S_AXI_GP1_BREADY,
|
|
input S_AXI_GP1_RREADY,
|
|
input S_AXI_GP1_WLAST,
|
|
input S_AXI_GP1_WVALID,
|
|
input [1:0] S_AXI_GP1_ARBURST,
|
|
input [1:0] S_AXI_GP1_ARLOCK,
|
|
input [2:0] S_AXI_GP1_ARSIZE,
|
|
input [1:0] S_AXI_GP1_AWBURST,
|
|
input [1:0] S_AXI_GP1_AWLOCK,
|
|
input [2:0] S_AXI_GP1_AWSIZE,
|
|
input [2:0] S_AXI_GP1_ARPROT,
|
|
input [2:0] S_AXI_GP1_AWPROT,
|
|
input [31:0] S_AXI_GP1_ARADDR,
|
|
input [31:0] S_AXI_GP1_AWADDR,
|
|
input [31:0] S_AXI_GP1_WDATA,
|
|
input [3:0] S_AXI_GP1_ARCACHE,
|
|
input [3:0] S_AXI_GP1_ARLEN,
|
|
input [3:0] S_AXI_GP1_ARQOS,
|
|
input [3:0] S_AXI_GP1_AWCACHE,
|
|
input [3:0] S_AXI_GP1_AWLEN,
|
|
input [3:0] S_AXI_GP1_AWQOS,
|
|
input [3:0] S_AXI_GP1_WSTRB,
|
|
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
|
|
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
|
|
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
|
|
|
|
//S_AXI_ACP
|
|
|
|
// -- Output
|
|
|
|
output S_AXI_ACP_ARESETN,
|
|
output S_AXI_ACP_ARREADY,
|
|
output S_AXI_ACP_AWREADY,
|
|
output S_AXI_ACP_BVALID,
|
|
output S_AXI_ACP_RLAST,
|
|
output S_AXI_ACP_RVALID,
|
|
output S_AXI_ACP_WREADY,
|
|
output [1:0] S_AXI_ACP_BRESP,
|
|
output [1:0] S_AXI_ACP_RRESP,
|
|
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
|
|
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
|
|
output [63:0] S_AXI_ACP_RDATA,
|
|
|
|
// -- Input
|
|
|
|
input S_AXI_ACP_ACLK,
|
|
input S_AXI_ACP_ARVALID,
|
|
input S_AXI_ACP_AWVALID,
|
|
input S_AXI_ACP_BREADY,
|
|
input S_AXI_ACP_RREADY,
|
|
input S_AXI_ACP_WLAST,
|
|
input S_AXI_ACP_WVALID,
|
|
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
|
|
input [2:0] S_AXI_ACP_ARPROT,
|
|
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
|
|
input [2:0] S_AXI_ACP_AWPROT,
|
|
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
|
|
input [31:0] S_AXI_ACP_ARADDR,
|
|
input [31:0] S_AXI_ACP_AWADDR,
|
|
input [3:0] S_AXI_ACP_ARCACHE,
|
|
input [3:0] S_AXI_ACP_ARLEN,
|
|
input [3:0] S_AXI_ACP_ARQOS,
|
|
input [3:0] S_AXI_ACP_AWCACHE,
|
|
input [3:0] S_AXI_ACP_AWLEN,
|
|
input [3:0] S_AXI_ACP_AWQOS,
|
|
input [1:0] S_AXI_ACP_ARBURST,
|
|
input [1:0] S_AXI_ACP_ARLOCK,
|
|
input [2:0] S_AXI_ACP_ARSIZE,
|
|
input [1:0] S_AXI_ACP_AWBURST,
|
|
input [1:0] S_AXI_ACP_AWLOCK,
|
|
input [2:0] S_AXI_ACP_AWSIZE,
|
|
input [4:0] S_AXI_ACP_ARUSER,
|
|
input [4:0] S_AXI_ACP_AWUSER,
|
|
input [63:0] S_AXI_ACP_WDATA,
|
|
input [7:0] S_AXI_ACP_WSTRB,
|
|
|
|
// S_AXI_HP_0
|
|
|
|
// -- Output
|
|
output S_AXI_HP0_ARESETN,
|
|
output S_AXI_HP0_ARREADY,
|
|
output S_AXI_HP0_AWREADY,
|
|
output S_AXI_HP0_BVALID,
|
|
output S_AXI_HP0_RLAST,
|
|
output S_AXI_HP0_RVALID,
|
|
output S_AXI_HP0_WREADY,
|
|
output [1:0] S_AXI_HP0_BRESP,
|
|
output [1:0] S_AXI_HP0_RRESP,
|
|
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
|
|
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
|
|
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
|
|
output [7:0] S_AXI_HP0_RCOUNT,
|
|
output [7:0] S_AXI_HP0_WCOUNT,
|
|
output [2:0] S_AXI_HP0_RACOUNT,
|
|
output [5:0] S_AXI_HP0_WACOUNT,
|
|
|
|
// -- Input
|
|
input S_AXI_HP0_ACLK,
|
|
input S_AXI_HP0_ARVALID,
|
|
input S_AXI_HP0_AWVALID,
|
|
input S_AXI_HP0_BREADY,
|
|
input S_AXI_HP0_RDISSUECAP1_EN,
|
|
input S_AXI_HP0_RREADY,
|
|
input S_AXI_HP0_WLAST,
|
|
input S_AXI_HP0_WRISSUECAP1_EN,
|
|
input S_AXI_HP0_WVALID,
|
|
input [1:0] S_AXI_HP0_ARBURST,
|
|
input [1:0] S_AXI_HP0_ARLOCK,
|
|
input [2:0] S_AXI_HP0_ARSIZE,
|
|
input [1:0] S_AXI_HP0_AWBURST,
|
|
input [1:0] S_AXI_HP0_AWLOCK,
|
|
input [2:0] S_AXI_HP0_AWSIZE,
|
|
input [2:0] S_AXI_HP0_ARPROT,
|
|
input [2:0] S_AXI_HP0_AWPROT,
|
|
input [31:0] S_AXI_HP0_ARADDR,
|
|
input [31:0] S_AXI_HP0_AWADDR,
|
|
input [3:0] S_AXI_HP0_ARCACHE,
|
|
input [3:0] S_AXI_HP0_ARLEN,
|
|
input [3:0] S_AXI_HP0_ARQOS,
|
|
input [3:0] S_AXI_HP0_AWCACHE,
|
|
input [3:0] S_AXI_HP0_AWLEN,
|
|
input [3:0] S_AXI_HP0_AWQOS,
|
|
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
|
|
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
|
|
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
|
|
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
|
|
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
|
|
|
|
// S_AXI_HP1
|
|
// -- Output
|
|
output S_AXI_HP1_ARESETN,
|
|
output S_AXI_HP1_ARREADY,
|
|
output S_AXI_HP1_AWREADY,
|
|
output S_AXI_HP1_BVALID,
|
|
output S_AXI_HP1_RLAST,
|
|
output S_AXI_HP1_RVALID,
|
|
output S_AXI_HP1_WREADY,
|
|
output [1:0] S_AXI_HP1_BRESP,
|
|
output [1:0] S_AXI_HP1_RRESP,
|
|
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
|
|
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
|
|
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
|
|
output [7:0] S_AXI_HP1_RCOUNT,
|
|
output [7:0] S_AXI_HP1_WCOUNT,
|
|
output [2:0] S_AXI_HP1_RACOUNT,
|
|
output [5:0] S_AXI_HP1_WACOUNT,
|
|
|
|
|
|
// -- Input
|
|
input S_AXI_HP1_ACLK,
|
|
input S_AXI_HP1_ARVALID,
|
|
input S_AXI_HP1_AWVALID,
|
|
input S_AXI_HP1_BREADY,
|
|
input S_AXI_HP1_RDISSUECAP1_EN,
|
|
input S_AXI_HP1_RREADY,
|
|
input S_AXI_HP1_WLAST,
|
|
input S_AXI_HP1_WRISSUECAP1_EN,
|
|
input S_AXI_HP1_WVALID,
|
|
input [1:0] S_AXI_HP1_ARBURST,
|
|
input [1:0] S_AXI_HP1_ARLOCK,
|
|
input [2:0] S_AXI_HP1_ARSIZE,
|
|
input [1:0] S_AXI_HP1_AWBURST,
|
|
input [1:0] S_AXI_HP1_AWLOCK,
|
|
input [2:0] S_AXI_HP1_AWSIZE,
|
|
input [2:0] S_AXI_HP1_ARPROT,
|
|
input [2:0] S_AXI_HP1_AWPROT,
|
|
input [31:0] S_AXI_HP1_ARADDR,
|
|
input [31:0] S_AXI_HP1_AWADDR,
|
|
input [3:0] S_AXI_HP1_ARCACHE,
|
|
input [3:0] S_AXI_HP1_ARLEN,
|
|
input [3:0] S_AXI_HP1_ARQOS,
|
|
input [3:0] S_AXI_HP1_AWCACHE,
|
|
input [3:0] S_AXI_HP1_AWLEN,
|
|
input [3:0] S_AXI_HP1_AWQOS,
|
|
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
|
|
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
|
|
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
|
|
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
|
|
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
|
|
|
|
// S_AXI_HP2
|
|
// -- Output
|
|
output S_AXI_HP2_ARESETN,
|
|
output S_AXI_HP2_ARREADY,
|
|
output S_AXI_HP2_AWREADY,
|
|
output S_AXI_HP2_BVALID,
|
|
output S_AXI_HP2_RLAST,
|
|
output S_AXI_HP2_RVALID,
|
|
output S_AXI_HP2_WREADY,
|
|
output [1:0] S_AXI_HP2_BRESP,
|
|
output [1:0] S_AXI_HP2_RRESP,
|
|
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
|
|
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
|
|
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
|
|
output [7:0] S_AXI_HP2_RCOUNT,
|
|
output [7:0] S_AXI_HP2_WCOUNT,
|
|
output [2:0] S_AXI_HP2_RACOUNT,
|
|
output [5:0] S_AXI_HP2_WACOUNT,
|
|
|
|
|
|
// -- Input
|
|
input S_AXI_HP2_ACLK,
|
|
input S_AXI_HP2_ARVALID,
|
|
input S_AXI_HP2_AWVALID,
|
|
input S_AXI_HP2_BREADY,
|
|
input S_AXI_HP2_RDISSUECAP1_EN,
|
|
input S_AXI_HP2_RREADY,
|
|
input S_AXI_HP2_WLAST,
|
|
input S_AXI_HP2_WRISSUECAP1_EN,
|
|
input S_AXI_HP2_WVALID,
|
|
input [1:0] S_AXI_HP2_ARBURST,
|
|
input [1:0] S_AXI_HP2_ARLOCK,
|
|
input [2:0] S_AXI_HP2_ARSIZE,
|
|
input [1:0] S_AXI_HP2_AWBURST,
|
|
input [1:0] S_AXI_HP2_AWLOCK,
|
|
input [2:0] S_AXI_HP2_AWSIZE,
|
|
input [2:0] S_AXI_HP2_ARPROT,
|
|
input [2:0] S_AXI_HP2_AWPROT,
|
|
input [31:0] S_AXI_HP2_ARADDR,
|
|
input [31:0] S_AXI_HP2_AWADDR,
|
|
input [3:0] S_AXI_HP2_ARCACHE,
|
|
input [3:0] S_AXI_HP2_ARLEN,
|
|
input [3:0] S_AXI_HP2_ARQOS,
|
|
input [3:0] S_AXI_HP2_AWCACHE,
|
|
input [3:0] S_AXI_HP2_AWLEN,
|
|
input [3:0] S_AXI_HP2_AWQOS,
|
|
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
|
|
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
|
|
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
|
|
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
|
|
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
|
|
|
|
// S_AXI_HP_3
|
|
|
|
// -- Output
|
|
output S_AXI_HP3_ARESETN,
|
|
output S_AXI_HP3_ARREADY,
|
|
output S_AXI_HP3_AWREADY,
|
|
output S_AXI_HP3_BVALID,
|
|
output S_AXI_HP3_RLAST,
|
|
output S_AXI_HP3_RVALID,
|
|
output S_AXI_HP3_WREADY,
|
|
output [1:0] S_AXI_HP3_BRESP,
|
|
output [1:0] S_AXI_HP3_RRESP,
|
|
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
|
|
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
|
|
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
|
|
output [7:0] S_AXI_HP3_RCOUNT,
|
|
output [7:0] S_AXI_HP3_WCOUNT,
|
|
output [2:0] S_AXI_HP3_RACOUNT,
|
|
output [5:0] S_AXI_HP3_WACOUNT,
|
|
|
|
|
|
// -- Input
|
|
input S_AXI_HP3_ACLK,
|
|
input S_AXI_HP3_ARVALID,
|
|
input S_AXI_HP3_AWVALID,
|
|
input S_AXI_HP3_BREADY,
|
|
input S_AXI_HP3_RDISSUECAP1_EN,
|
|
input S_AXI_HP3_RREADY,
|
|
input S_AXI_HP3_WLAST,
|
|
input S_AXI_HP3_WRISSUECAP1_EN,
|
|
input S_AXI_HP3_WVALID,
|
|
input [1:0] S_AXI_HP3_ARBURST,
|
|
input [1:0] S_AXI_HP3_ARLOCK,
|
|
input [2:0] S_AXI_HP3_ARSIZE,
|
|
input [1:0] S_AXI_HP3_AWBURST,
|
|
input [1:0] S_AXI_HP3_AWLOCK,
|
|
input [2:0] S_AXI_HP3_AWSIZE,
|
|
input [2:0] S_AXI_HP3_ARPROT,
|
|
input [2:0] S_AXI_HP3_AWPROT,
|
|
input [31:0] S_AXI_HP3_ARADDR,
|
|
input [31:0] S_AXI_HP3_AWADDR,
|
|
input [3:0] S_AXI_HP3_ARCACHE,
|
|
input [3:0] S_AXI_HP3_ARLEN,
|
|
input [3:0] S_AXI_HP3_ARQOS,
|
|
input [3:0] S_AXI_HP3_AWCACHE,
|
|
input [3:0] S_AXI_HP3_AWLEN,
|
|
input [3:0] S_AXI_HP3_AWQOS,
|
|
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
|
|
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
|
|
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
|
|
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
|
|
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
|
|
|
|
//FIO ========================================
|
|
|
|
//IRQ
|
|
output IRQ_P2F_DMAC_ABORT ,
|
|
output IRQ_P2F_DMAC0,
|
|
output IRQ_P2F_DMAC1,
|
|
output IRQ_P2F_DMAC2,
|
|
output IRQ_P2F_DMAC3,
|
|
output IRQ_P2F_DMAC4,
|
|
output IRQ_P2F_DMAC5,
|
|
output IRQ_P2F_DMAC6,
|
|
output IRQ_P2F_DMAC7,
|
|
output IRQ_P2F_SMC,
|
|
output IRQ_P2F_QSPI,
|
|
output IRQ_P2F_CTI,
|
|
output IRQ_P2F_GPIO,
|
|
output IRQ_P2F_USB0,
|
|
output IRQ_P2F_ENET0,
|
|
output IRQ_P2F_ENET_WAKE0,
|
|
output IRQ_P2F_SDIO0,
|
|
output IRQ_P2F_I2C0,
|
|
output IRQ_P2F_SPI0,
|
|
output IRQ_P2F_UART0,
|
|
output IRQ_P2F_CAN0,
|
|
output IRQ_P2F_USB1,
|
|
output IRQ_P2F_ENET1,
|
|
output IRQ_P2F_ENET_WAKE1,
|
|
output IRQ_P2F_SDIO1,
|
|
output IRQ_P2F_I2C1,
|
|
output IRQ_P2F_SPI1,
|
|
output IRQ_P2F_UART1,
|
|
output IRQ_P2F_CAN1,
|
|
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
|
|
input Core0_nFIQ,
|
|
input Core0_nIRQ,
|
|
input Core1_nFIQ,
|
|
input Core1_nIRQ,
|
|
|
|
//DMA
|
|
|
|
output [1:0] DMA0_DATYPE,
|
|
output DMA0_DAVALID,
|
|
output DMA0_DRREADY,
|
|
output DMA0_RSTN,
|
|
output [1:0] DMA1_DATYPE,
|
|
output DMA1_DAVALID,
|
|
output DMA1_DRREADY,
|
|
output DMA1_RSTN,
|
|
output [1:0] DMA2_DATYPE,
|
|
output DMA2_DAVALID,
|
|
output DMA2_DRREADY,
|
|
output DMA2_RSTN,
|
|
output [1:0] DMA3_DATYPE,
|
|
output DMA3_DAVALID,
|
|
output DMA3_DRREADY,
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output DMA3_RSTN,
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input DMA0_ACLK,
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input DMA0_DAREADY,
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input DMA0_DRLAST,
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input DMA0_DRVALID,
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input DMA1_ACLK,
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input DMA1_DAREADY,
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input DMA1_DRLAST,
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input DMA1_DRVALID,
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input DMA2_ACLK,
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input DMA2_DAREADY,
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input DMA2_DRLAST,
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input DMA2_DRVALID,
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input DMA3_ACLK,
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input DMA3_DAREADY,
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input DMA3_DRLAST,
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input DMA3_DRVALID,
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input [1:0] DMA0_DRTYPE,
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input [1:0] DMA1_DRTYPE,
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input [1:0] DMA2_DRTYPE,
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input [1:0] DMA3_DRTYPE,
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//FCLK
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output FCLK_CLK3,
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output FCLK_CLK2,
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output FCLK_CLK1,
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output FCLK_CLK0,
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input FCLK_CLKTRIG3_N,
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input FCLK_CLKTRIG2_N,
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input FCLK_CLKTRIG1_N,
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input FCLK_CLKTRIG0_N,
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output FCLK_RESET3_N,
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output FCLK_RESET2_N,
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output FCLK_RESET1_N,
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output FCLK_RESET0_N,
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//FTMD
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input [31:0] FTMD_TRACEIN_DATA,
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input FTMD_TRACEIN_VALID,
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input FTMD_TRACEIN_CLK,
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input [3:0] FTMD_TRACEIN_ATID,
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//FTMT
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input FTMT_F2P_TRIG_0,
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output FTMT_F2P_TRIGACK_0,
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input FTMT_F2P_TRIG_1,
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output FTMT_F2P_TRIGACK_1,
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input FTMT_F2P_TRIG_2,
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output FTMT_F2P_TRIGACK_2,
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input FTMT_F2P_TRIG_3,
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output FTMT_F2P_TRIGACK_3,
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input [31:0] FTMT_F2P_DEBUG,
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input FTMT_P2F_TRIGACK_0,
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output FTMT_P2F_TRIG_0,
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input FTMT_P2F_TRIGACK_1,
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output FTMT_P2F_TRIG_1,
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input FTMT_P2F_TRIGACK_2,
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output FTMT_P2F_TRIG_2,
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input FTMT_P2F_TRIGACK_3,
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output FTMT_P2F_TRIG_3,
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output [31:0] FTMT_P2F_DEBUG,
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//FIDLE
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input FPGA_IDLE_N,
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//EVENT
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output EVENT_EVENTO,
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output [1:0] EVENT_STANDBYWFE,
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output [1:0] EVENT_STANDBYWFI,
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input EVENT_EVENTI,
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//DARB
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input [3:0] DDR_ARB,
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inout [C_MIO_PRIMITIVE - 1:0] MIO,
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//DDR
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inout DDR_CAS_n, // CASB
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inout DDR_CKE, // CKE
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inout DDR_Clk_n, // CKN
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inout DDR_Clk, // CKP
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inout DDR_CS_n, // CSB
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inout DDR_DRSTB, // DDR_DRSTB
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inout DDR_ODT, // ODT
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inout DDR_RAS_n, // RASB
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|
inout DDR_WEB,
|
|
inout [2:0] DDR_BankAddr, // BA
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inout [14:0] DDR_Addr, // A
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|
|
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inout DDR_VRN,
|
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inout DDR_VRP,
|
|
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
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inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
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|
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
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inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
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|
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inout PS_SRSTB, // SRSTB
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inout PS_CLK, // CLK
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inout PS_PORB // PORB
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);
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endmodule // processing_system7
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