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494 lines
19 KiB
Verilog
494 lines
19 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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/*
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########################################################################
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Epiphany eLink AXI Master Module
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########################################################################
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*/
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`define WRITE_BIT 102
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`define DATAMODE_RANGE 101:100
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`define CTRLMODE_RANGE 99:96
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`define DSTADDR_RANGE 95:64
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`define DSTADDR_LSB 64
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`define SRCADDR_RANGE 63:32
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`define SRCADDR_LSB 32
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`define DATA_RANGE 31:0
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`define DATA_LSB 0
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`timescale 1 ns / 1 ps
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module emaxi_v1_0_M00_AXI #
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(
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// Users to add parameters here
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Base address of targeted slave
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parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
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// Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
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parameter integer C_M_AXI_BURST_LEN = 16,
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// Thread ID Width
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parameter integer C_M_AXI_ID_WIDTH = 1,
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// Width of Address Bus
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parameter integer C_M_AXI_ADDR_WIDTH = 32,
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// Width of Data Bus
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parameter integer C_M_AXI_DATA_WIDTH = 64,
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// Width of User Write Address Bus
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parameter integer C_M_AXI_AWUSER_WIDTH = 0,
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// Width of User Read Address Bus
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parameter integer C_M_AXI_ARUSER_WIDTH = 0,
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// Width of User Write Data Bus
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parameter integer C_M_AXI_WUSER_WIDTH = 0,
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// Width of User Read Data Bus
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parameter integer C_M_AXI_RUSER_WIDTH = 0,
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// Width of User Response Bus
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parameter integer C_M_AXI_BUSER_WIDTH = 0
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)
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(
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// Users to add ports here
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// FIFO read-master port, writes from RX channel
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input wire [102:0] emwr_rd_data,
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output wire emwr_rd_en,
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input wire emwr_empty,
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// FIFO read-master port, read requests from RX channel
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input wire [102:0] emrq_rd_data,
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output wire emrq_rd_en,
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input wire emrq_empty,
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// FIFO write-master port, read responses to TX channel
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output reg [102:0] emrr_wr_data,
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output reg emrr_wr_en,
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input wire emrr_full,
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input wire emrr_prog_full,
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// User ports ends
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// Do not modify the ports beyond this line
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// Global Clock Signal.
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input wire M_AXI_ACLK,
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// Global Reset Singal. This Signal is Active Low
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input wire M_AXI_ARESETN,
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// Master Interface Write Address ID
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output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
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// Master Interface Write Address
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output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
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// Burst length. The burst length gives the exact number of transfers in a burst
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output wire [7 : 0] M_AXI_AWLEN,
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// Burst size. This signal indicates the size of each transfer in the burst
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output wire [2 : 0] M_AXI_AWSIZE,
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// Burst type. The burst type and the size information,
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// determine how the address for each transfer within the burst is calculated.
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output wire [1 : 0] M_AXI_AWBURST,
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// Lock type. Provides additional information about the
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// atomic characteristics of the transfer.
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output wire M_AXI_AWLOCK,
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// Memory type. This signal indicates how transactions
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// are required to progress through a system.
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output wire [3 : 0] M_AXI_AWCACHE,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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output wire [2 : 0] M_AXI_AWPROT,
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// Quality of Service, QoS identifier sent for each write transaction.
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output wire [3 : 0] M_AXI_AWQOS,
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// Optional User-defined signal in the write address channel.
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output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
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// Write address valid. This signal indicates that
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// the channel is signaling valid write address and control information.
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output wire M_AXI_AWVALID,
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// Write address ready. This signal indicates that
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// the slave is ready to accept an address and associated control signals
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input wire M_AXI_AWREADY,
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// Master Interface Write Data.
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output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
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// Write strobes. This signal indicates which byte
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// lanes hold valid data. There is one write strobe
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// bit for each eight bits of the write data bus.
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output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
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// Write last. This signal indicates the last transfer in a write burst.
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output wire M_AXI_WLAST,
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// Optional User-defined signal in the write data channel.
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output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
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// Write valid. This signal indicates that valid write
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// data and strobes are available
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output wire M_AXI_WVALID,
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// Write ready. This signal indicates that the slave
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// can accept the write data.
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input wire M_AXI_WREADY,
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// Master Interface Write Response.
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input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
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// Write response. This signal indicates the status of the write transaction.
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input wire [1 : 0] M_AXI_BRESP,
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// Optional User-defined signal in the write response channel
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input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
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// Write response valid. This signal indicates that the
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// channel is signaling a valid write response.
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input wire M_AXI_BVALID,
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// Response ready. This signal indicates that the master
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// can accept a write response.
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output wire M_AXI_BREADY,
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// Master Interface Read Address.
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output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
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// Read address. This signal indicates the initial
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// address of a read burst transaction.
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output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
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// Burst length. The burst length gives the exact number of transfers in a burst
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output wire [7 : 0] M_AXI_ARLEN,
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// Burst size. This signal indicates the size of each transfer in the burst
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output wire [2 : 0] M_AXI_ARSIZE,
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// Burst type. The burst type and the size information,
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// determine how the address for each transfer within the burst is calculated.
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output wire [1 : 0] M_AXI_ARBURST,
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// Lock type. Provides additional information about the
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// atomic characteristics of the transfer.
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output wire M_AXI_ARLOCK,
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// Memory type. This signal indicates how transactions
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// are required to progress through a system.
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output wire [3 : 0] M_AXI_ARCACHE,
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// Protection type. This signal indicates the privilege
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// and security level of the transaction, and whether
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// the transaction is a data access or an instruction access.
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output wire [2 : 0] M_AXI_ARPROT,
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// Quality of Service, QoS identifier sent for each read transaction
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output wire [3 : 0] M_AXI_ARQOS,
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// Optional User-defined signal in the read address channel.
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output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
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// Write address valid. This signal indicates that
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// the channel is signaling valid read address and control information
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output wire M_AXI_ARVALID,
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// Read address ready. This signal indicates that
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// the slave is ready to accept an address and associated control signals
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input wire M_AXI_ARREADY,
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// Read ID tag. This signal is the identification tag
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// for the read data group of signals generated by the slave.
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input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
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// Master Read Data
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input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
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// Read response. This signal indicates the status of the read transfer
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input wire [1 : 0] M_AXI_RRESP,
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// Read last. This signal indicates the last transfer in a read burst
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input wire M_AXI_RLAST,
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// Optional User-defined signal in the read address channel.
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input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
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// Read valid. This signal indicates that the channel
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// is signaling the required read data.
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input wire M_AXI_RVALID,
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// Read ready. This signal indicates that the master can
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// accept the read data and response information.
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output wire M_AXI_RREADY
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);
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// function called clogb2 that returns an integer which has the
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//value of the ceiling of the log base 2
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// function called clogb2 that returns an integer which has the
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// value of the ceiling of the log base 2.
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function integer clogb2 (input integer bit_depth);
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begin
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for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
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bit_depth = bit_depth >> 1;
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end
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endfunction // clogb2
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// AXI4LITE signals
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//AXI4 internal temp signals
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reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
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reg [7:0] axi_awlen;
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reg [2:0] axi_awsize;
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reg axi_awvalid;
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reg [C_M_AXI_DATA_WIDTH-1 : 0] axi_wdata;
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reg [C_M_AXI_DATA_WIDTH/8-1 : 0] axi_wstrb;
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reg axi_wlast;
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reg axi_wvalid;
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//reg axi_bready;
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reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
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reg [7:0] axi_arlen;
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reg [2:0] axi_arsize;
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reg axi_arvalid;
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wire axi_rready;
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// I/O Connections assignments
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//I/O Connections. Write Address (AW)
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assign M_AXI_AWID = 'b0;
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//The AXI address is a concatenation of the target base address + active offset range
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assign M_AXI_AWADDR = axi_awaddr;
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//Burst LENgth is number of transaction beats, minus 1
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assign M_AXI_AWLEN = axi_awlen;
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//Size should be C_M_AXI_DATA_WIDTH, in 2^SIZE bytes, otherwise narrow bursts are used
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assign M_AXI_AWSIZE = axi_awsize;
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//INCR burst type is usually used, except for keyhole bursts
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assign M_AXI_AWBURST = 2'b01;
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assign M_AXI_AWLOCK = 1'b0;
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//Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
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assign M_AXI_AWCACHE = 4'b0010;
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assign M_AXI_AWPROT = 3'h0;
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assign M_AXI_AWQOS = 4'h0;
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assign M_AXI_AWUSER = 'b1;
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assign M_AXI_AWVALID = axi_awvalid;
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//Write Data(W)
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assign M_AXI_WDATA = axi_wdata;
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//All bursts are complete and aligned in this example
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assign M_AXI_WSTRB = axi_wstrb;
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assign M_AXI_WLAST = axi_wlast;
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assign M_AXI_WUSER = 'b0;
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assign M_AXI_WVALID = axi_wvalid;
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//Write Response (B)
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assign M_AXI_BREADY = 1'b1; // axi_bready;
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//Read Address (AR)
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assign M_AXI_ARID = 'b0;
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assign M_AXI_ARADDR = axi_araddr;
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//Burst LENgth is number of transaction beats, minus 1
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assign M_AXI_ARLEN = axi_arlen;
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//Size should be C_M_AXI_DATA_WIDTH, in 2^n bytes, otherwise narrow bursts are used
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assign M_AXI_ARSIZE = axi_arsize;
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//INCR burst type is usually used, except for keyhole bursts
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assign M_AXI_ARBURST = 2'b01;
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assign M_AXI_ARLOCK = 1'b0;
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//Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache.
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assign M_AXI_ARCACHE = 4'b0010;
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assign M_AXI_ARPROT = 3'h0;
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assign M_AXI_ARQOS = 4'h0;
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assign M_AXI_ARUSER = 'b1;
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assign M_AXI_ARVALID = axi_arvalid;
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//Read and Read Response (R)
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assign M_AXI_RREADY = axi_rready;
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//--------------------
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//Write Address Channel
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//--------------------
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reg aw_wait;
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reg w_wait;
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assign emwr_rd_en = ( ~emwr_empty & ~axi_awvalid & ~axi_wvalid )
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| ( ~emwr_empty & axi_awvalid & M_AXI_AWREADY & axi_wvalid & M_AXI_WREADY)
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| ( ~emwr_empty & axi_awvalid & M_AXI_AWREADY & w_wait )
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| ( ~emwr_empty & axi_wvalid & M_AXI_WREADY & aw_wait );
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// Generate valid signals, internal waits
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always @( posedge M_AXI_ACLK ) begin
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if( M_AXI_ARESETN == 1'b0 ) begin
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axi_awvalid <= 1'b0;
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axi_wvalid <= 1'b0;
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aw_wait <= 1'b0;
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w_wait <= 1'b0;
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end else begin
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if( ~axi_awvalid & emwr_rd_en )
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axi_awvalid <= 1'b1;
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else if( axi_awvalid & M_AXI_AWREADY & ( emwr_empty | aw_wait ))
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axi_awvalid <= 1'b0;
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if( ~emwr_empty & axi_awvalid & M_AXI_AWREADY & ~M_AXI_WREADY )
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aw_wait <= 1'b1;
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else if( emwr_rd_en )
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aw_wait <= 1'b0;
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if( ~axi_wvalid & emwr_rd_en )
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axi_wvalid <= 1'b1;
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else if( axi_wvalid & M_AXI_WREADY & ( emwr_empty | w_wait ))
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axi_wvalid <= 1'b0;
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if( ~emwr_empty & axi_wvalid & M_AXI_WREADY & ~M_AXI_AWREADY )
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w_wait <= 1'b1;
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else if( emwr_rd_en )
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w_wait <= 1'b0;
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end // else: !if( M_AXI_ARESETN == 1'b0 )
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end // always @ ( posedge M_AXI_ACLK )
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// Put the address, info, & data on the AXI signals
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always @( posedge M_AXI_ACLK ) begin
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if( M_AXI_ARESETN == 1'b0 ) begin
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axi_awaddr <= 'd0;
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axi_awlen <= 'd0;
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axi_awsize <= 'd0;
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axi_wdata <= 'd0;
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axi_wstrb <= 'd0;
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axi_wlast <= 1'b1; // TODO: no bursts for now
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end else begin
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if( ~axi_awvalid | M_AXI_AWREADY ) begin
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axi_awaddr <= emwr_rd_data[`DSTADDR_RANGE];
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axi_awlen <= 'd0;
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axi_awsize <= {1'b0, emwr_rd_data[`DATAMODE_RANGE]};
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end
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if( ~axi_wvalid | M_AXI_WREADY ) begin
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// Place data of stated size in all legal positions
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case( emwr_rd_data[`DATAMODE_RANGE] )
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2'd0: axi_wdata <= { 8{emwr_rd_data[`DATA_LSB+7 -: 8]}};
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2'd1: axi_wdata <= { 4{emwr_rd_data[`DATA_LSB+15 -: 16]}};
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2'd2: axi_wdata <= { 2{emwr_rd_data[`DATA_LSB+31 -: 32]}};
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default: axi_wdata <= { emwr_rd_data[`SRCADDR_RANGE],
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emwr_rd_data[`DATA_RANGE]};
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endcase // case ( emwr_rd_data[`DATAMODE_RANGE] )
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// Create write strobes
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case( emwr_rd_data[`DATAMODE_RANGE] )
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2'd0: // BYTE
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case( emwr_rd_data[`DSTADDR_LSB+2 -: 3] )
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3'd0: axi_wstrb <= 8'h01;
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3'd1: axi_wstrb <= 8'h02;
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3'd2: axi_wstrb <= 8'h04;
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3'd3: axi_wstrb <= 8'h08;
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3'd4: axi_wstrb <= 8'h10;
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3'd5: axi_wstrb <= 8'h20;
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3'd6: axi_wstrb <= 8'h40;
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default: axi_wstrb <= 8'h80;
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endcase
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2'd1: // 16b HWORD
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case( emwr_rd_data[`DSTADDR_LSB+2 -: 2] )
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2'd0: axi_wstrb <= 8'h03;
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2'd1: axi_wstrb <= 8'h0C;
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2'd2: axi_wstrb <= 8'h30;
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default: axi_wstrb <= 8'hC0;
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endcase
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2'd2: // 32b WORD
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if( emwr_rd_data[`DSTADDR_LSB+2] )
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axi_wstrb <= 8'hF0;
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else
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axi_wstrb <= 8'h0F;
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default: // 64b DWORD
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axi_wstrb <= 8'hFF;
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endcase // case ( emwr_rd_data[`DATAMODE_RANGE] )
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end // if ( ~axi_wvalid | M_AXI_WREADY )
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end // else: !if( M_AXI_ARESETN == 1'b0 )
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end // always @ ( posedge M_AXI_ACLK )
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//----------------------------
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// Read Address Channel
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//----------------------------
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reg read_waiting;
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assign emrq_rd_en = axi_rready & M_AXI_RVALID;
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always @( posedge M_AXI_ACLK ) begin
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if ( ~M_AXI_ARESETN ) begin
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axi_araddr <= 'd0;
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axi_arlen <= 'd0;
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axi_arsize <= 'd0;
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axi_arvalid <= 1'b0;
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read_waiting <= 1'b0;
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end else begin
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if( ~emrq_empty & ~read_waiting ) begin
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axi_arvalid <= 1'b1;
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axi_arsize <= {1'b0, emrq_rd_data[`DATAMODE_RANGE]};
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axi_araddr <= emrq_rd_data[`DSTADDR_RANGE];
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end else if( M_AXI_ARREADY ) begin
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axi_arvalid <= 1'b0;
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end
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if( ~emrq_empty & ~read_waiting )
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read_waiting <= 1'b1;
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else if( axi_rready & M_AXI_RVALID )
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read_waiting <= 1'b0;
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end
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end // always @ ( posedge M_AXI_ACLK )
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//--------------------------------
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// Read Data (and Response) Channel
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//--------------------------------
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assign axi_rready = ~emrr_full;
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always @( posedge M_AXI_ACLK ) begin
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if( ~M_AXI_ARESETN ) begin
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emrr_wr_data <= 'd0;
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emrr_wr_en <= 1'b0;
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end else begin
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emrr_wr_en <= axi_rready & M_AXI_RVALID;
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emrr_wr_data[`WRITE_BIT] <= 1'b1;
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emrr_wr_data[`DATAMODE_RANGE] <= emrq_rd_data[`DATAMODE_RANGE];
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emrr_wr_data[`CTRLMODE_RANGE] <= emrq_rd_data[`CTRLMODE_RANGE]; // TODO: This or cfg value?
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emrr_wr_data[`DSTADDR_RANGE] <= emrq_rd_data[`SRCADDR_RANGE];
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emrr_wr_data[`SRCADDR_RANGE] <= M_AXI_RDATA[63:32]; // only used for 64b reads
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emrr_wr_data[`DATA_RANGE] <= M_AXI_RDATA[31:0];
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// Steer read data according to size & host address lsbs
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case( emrq_rd_data[`DATAMODE_RANGE] )
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2'd0: // BYTE read
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case( emrq_rd_data[`DSTADDR_LSB+2 -: 3] )
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3'd0: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[7:0];
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3'd1: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[15:8];
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3'd2: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[23:16];
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3'd3: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[31:24];
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3'd4: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[39:32];
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3'd5: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[47:40];
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3'd6: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[55:48];
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default: emrr_wr_data[`DATA_LSB+7 -: 8] <= M_AXI_RDATA[63:56];
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endcase // case ( emrq_rd_data[`DSTADDR_LSB+2 -: 3] )
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2'd1: // 16b HWORD
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case( emrq_rd_data[`DSTADDR_LSB+2 -: 2] )
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2'd0: emrr_wr_data[`DATA_LSB+15 -: 16] <= M_AXI_RDATA[15:0];
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2'd1: emrr_wr_data[`DATA_LSB+15 -: 16] <= M_AXI_RDATA[31:16];
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2'd2: emrr_wr_data[`DATA_LSB+15 -: 16] <= M_AXI_RDATA[47:32];
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default: emrr_wr_data[`DATA_LSB+15 -: 16] <= M_AXI_RDATA[63:48];
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endcase // case ( emrq_rd_data[`DSTADDR_LSB+2 -: 2] )
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2'd2: // 32b WORD
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if( emrq_rd_data[`DSTADDR_LSB+2] )
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emrr_wr_data[`DATA_RANGE] <= M_AXI_RDATA[63:32];
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// 32b w/0 offset handled by default
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// 64b word already defined by defaults above
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endcase
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end // else: !if( ~M_AXI_ARESETN )
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end // always @ ( posedge M_AXI_ACLK )
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endmodule
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