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19 lines
239 B
Verilog
19 lines
239 B
Verilog
module BUFR (/*AUTOARG*/
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// Outputs
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O,
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// Inputs
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I, CE, CLR
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);
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parameter BUFR_DIVIDE=0;
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parameter SIM_DEVICE=0;
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input I;
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input CE;
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input CLR;
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output O;
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assign O=I & CE & ~CLR;
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endmodule // IBUFDS
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