mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
23 lines
274 B
Verilog
23 lines
274 B
Verilog
module OBUFTDS (/*AUTOARG*/
|
|
// Outputs
|
|
O, OB,
|
|
// Inputs
|
|
I, T
|
|
);
|
|
|
|
parameter IOSTANDARD=0;
|
|
parameter SLEW=0;
|
|
|
|
|
|
input I;
|
|
input T;
|
|
output O;
|
|
output OB;
|
|
|
|
assign O = T ? 1'bz : I;
|
|
assign OB = T ? 1'bz : ~I;
|
|
|
|
|
|
endmodule // OBUFTDS
|
|
|