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https://github.com/aolofsson/oh.git
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c885745f6c
- Interrupted mid coding apparently.. - Upper bits need to be zeroed out for 8/16 bit read responses
520 lines
18 KiB
Verilog
520 lines
18 KiB
Verilog
/*
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########################################################################
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Epiphany eLink AXI Master Module
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########################################################################
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NOTES:
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--write channels: write address, write data, write response
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--read channels: read address, read data channel
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--'valid' source signal used to show valid address,data,control is available
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--'ready' destination ready signal indicates readyness to accept information
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--'last' signal indicates the transfer of final data item
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--read and write have separate address channels
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--read data channel carries read data from slave to master
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--write channel includes a byte lane strobe signal for every eight data bits
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--there is no acknowledge on write, treated as buffered
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--channels are unidirectional
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--valid is asserted uncondotionally
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--ready occurs cycle after valid
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--there can be no combinatorial path between input and output of interface
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--destination is permitted to wait for valud before asserting READY
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--source is not allowed to wait for READY to assert VALID
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--AWVALID must remain asserted until the rising clock edge after slave asserts AWREADY??
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--The default state of AWREADY can be either HIGH or LOW. This specification recommends a default state of HIGH.
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--During a write burst, the master can assert the WVALID signal only when it drives valid write data.
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--The default state of WREADY can be HIGH, but only if the slave can always accept write data in a single cycle.
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--The master must assert the WLAST signal while it is driving the final write transfer in the burst.
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--_aw=write address channel
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--_ar=read address channel
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--_r=read data channel
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--_w=write data channel
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--_b=write response channel
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*/
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module emaxi(/*autoarg*/
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// Outputs
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rxwr_wait, rxrd_wait, txrr_access, txrr_packet, m_axi_awid,
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m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
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m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
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m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
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m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
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m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
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m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
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// Inputs
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rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, txrr_wait,
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m_axi_aclk, m_axi_aresetn, m_axi_awready, m_axi_wready, m_axi_bid,
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m_axi_bresp, m_axi_bvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
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m_axi_rresp, m_axi_rlast, m_axi_rvalid
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);
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parameter M_IDW = 12;
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parameter PW = 104;
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parameter AW = 32;
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parameter DW = 32;
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//########################
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//ELINK INTERFACE
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//########################
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//Write request from erx
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input rxwr_access;
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input [PW-1:0] rxwr_packet;
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output rxwr_wait;
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//Read request from erx
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input rxrd_access;
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input [PW-1:0] rxrd_packet;
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output rxrd_wait;
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//Read respoonse for etx
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output txrr_access;
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output [PW-1:0] txrr_packet;
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input txrr_wait;
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//########################
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//AXI MASTER INTERFACE
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//########################
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input m_axi_aclk; // global clock signal.
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input m_axi_aresetn; // global reset singal.
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//Write address channel
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output [M_IDW-1:0] m_axi_awid; // write address ID
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output [31 : 0] m_axi_awaddr; // master interface write address
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output [7 : 0] m_axi_awlen; // burst length.
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output [2 : 0] m_axi_awsize; // burst size.
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output [1 : 0] m_axi_awburst; // burst type.
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output m_axi_awlock; // lock type
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output [3 : 0] m_axi_awcache; // memory type.
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output [2 : 0] m_axi_awprot; // protection type.
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output [3 : 0] m_axi_awqos; // quality of service
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output m_axi_awvalid; // write address valid
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input m_axi_awready; // write address ready
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//Write data channel
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output [M_IDW-1:0] m_axi_wid;
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output [63 : 0] m_axi_wdata; // master interface write data.
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output [7 : 0] m_axi_wstrb; // byte write strobes
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output m_axi_wlast; // indicates last transfer in a write burst.
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output m_axi_wvalid; // indicates data is ready to go
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input m_axi_wready; // indicates that the slave is ready for data
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//Write response channel
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input [M_IDW-1:0] m_axi_bid;
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input [1 : 0] m_axi_bresp; // status of the write transaction.
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input m_axi_bvalid; // channel is signaling a valid write response
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output m_axi_bready; // master can accept write response.
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//Read address channel
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output [M_IDW-1:0] m_axi_arid; // read address ID
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output [31 : 0] m_axi_araddr; // initial address of a read burst
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output [7 : 0] m_axi_arlen; // burst length
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output [2 : 0] m_axi_arsize; // burst size
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output [1 : 0] m_axi_arburst; // burst type
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output m_axi_arlock; //lock type
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output [3 : 0] m_axi_arcache; // memory type
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output [2 : 0] m_axi_arprot; // protection type
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output [3 : 0] m_axi_arqos; //
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output m_axi_arvalid; // valid read address and control information
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input m_axi_arready; // slave is ready to accept an address
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//Read data channel
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input [M_IDW-1:0] m_axi_rid;
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input [63 : 0] m_axi_rdata; // master read data
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input [1 : 0] m_axi_rresp; // status of the read transfer
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input m_axi_rlast; // signals last transfer in a read burst
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input m_axi_rvalid; // signaling the required read data
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output m_axi_rready; // master can accept the readback data
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//#########################################################################
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//REGISTER/WIRE DECLARATIONS
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//#########################################################################
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reg [31 : 0] m_axi_awaddr;
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reg [7:0] m_axi_awlen;
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reg [2:0] m_axi_awsize;
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reg m_axi_awvalid;
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reg [63 : 0] m_axi_wdata;
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reg [63 : 0] m_axi_rdata_reg;
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reg [7 : 0] m_axi_wstrb;
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reg m_axi_wlast;
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reg m_axi_wvalid;
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reg awvalid_b;
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reg [31:0] awaddr_b;
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reg [2:0] awsize_b;
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reg [7:0] awlen_b;
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reg wvalid_b;
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reg [63:0] wdata_b;
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reg [7:0] wstrb_b;
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reg [63 : 0] wdata_aligned;
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reg [7 : 0] wstrb_aligned;
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reg txrr_access;
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reg txrr_access_reg;
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reg [31:0] txrr_data;
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reg [31:0] txrr_srcaddr;
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//wires
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wire aw_go;
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wire w_go;
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wire readinfo_wren;
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wire readinfo_full;
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wire [47:0] readinfo_out;
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wire [47:0] readinfo_in;
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wire awvalid_in;
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wire [1:0] rxwr_datamode;
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wire [AW-1:0] rxwr_dstaddr;
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wire [DW-1:0] rxwr_data;
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wire [AW-1:0] rxwr_srcaddr;
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wire [1:0] rxrd_datamode;
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wire [3:0] rxrd_ctrlmode;
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wire [AW-1:0] rxrd_dstaddr;
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wire [AW-1:0] rxrd_srcaddr;
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wire [1:0] txrr_datamode;
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wire [3:0] txrr_ctrlmode;
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wire [31:0] txrr_dstaddr;
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//#########################################################################
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//EMESH 2 PACKET CONVERSION
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//#########################################################################
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//RXWR
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packet2emesh p2e_rxwr (
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// Outputs
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.write_out (),
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.datamode_out (rxwr_datamode[1:0]),
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.ctrlmode_out (),
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.dstaddr_out (rxwr_dstaddr[AW-1:0]),
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.data_out (rxwr_data[DW-1:0]),
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.srcaddr_out (rxwr_srcaddr[AW-1:0]),
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// Inputs
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.packet_in (rxwr_packet[PW-1:0])
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);
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//RXRD
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packet2emesh p2e_rxrd (
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// Outputs
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.write_out (),
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.datamode_out (rxrd_datamode[1:0]),
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.ctrlmode_out (rxrd_ctrlmode[3:0]),
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.dstaddr_out (rxrd_dstaddr[AW-1:0]),
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.data_out (),
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.srcaddr_out (rxrd_srcaddr[AW-1:0]),
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// Inputs
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.packet_in (rxrd_packet[PW-1:0])
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);
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//TXRR
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emesh2packet e2p (
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// Outputs
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.packet_out (txrr_packet[PW-1:0]),
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// Inputs
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.write_in (1'b1),
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.datamode_in (txrr_datamode[1:0]),
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.ctrlmode_in (txrr_ctrlmode[3:0]),
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.dstaddr_in (txrr_dstaddr[AW-1:0]),
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.data_in (txrr_data[DW-1:0]),
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.srcaddr_in (txrr_srcaddr[AW-1:0])
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);
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//#########################################################################
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//AXI unimplemented constants
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//#########################################################################
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//AW
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assign m_axi_awid[M_IDW-1:0] = {(M_IDW){1'b0}};
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assign m_axi_awburst[1:0] = 2'b01; //only increment burst supported
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assign m_axi_awcache[3:0] = 4'b0000;//TODO: correct value??
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assign m_axi_awprot[2:0] = 3'b000;
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assign m_axi_awqos[3:0] = 4'b0000;
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assign m_axi_awlock = 1'b0;
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//AR
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assign m_axi_arid[M_IDW-1:0] = {(M_IDW){1'b0}};
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assign m_axi_arburst[1:0] = 2'b01; //only increment burst supported
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assign m_axi_arcache[3:0] = 4'b0000;
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assign m_axi_arprot[2:0] = 3'h0;
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assign m_axi_arqos[3:0] = 4'h0;
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assign m_axi_arlock = 1'b0;
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//B
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assign m_axi_bready = 1'b1;//TODO: tie to wait signal????
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//W
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assign m_axi_wid[M_IDW-1:0] = {(M_IDW){1'b0}};
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//#########################################################################
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//Write address channel
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//#########################################################################
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assign aw_go = m_axi_awvalid & m_axi_awready;
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assign w_go = m_axi_wvalid & m_axi_wready;
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assign rxwr_wait = awvalid_b | wvalid_b;
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assign awvalid_in = rxwr_access & ~awvalid_b & ~wvalid_b;
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// generate write-address signals
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always @( posedge m_axi_aclk )
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if(!m_axi_aresetn)
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begin
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m_axi_awvalid <= 1'b0;
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m_axi_awaddr[31:0] <= 32'd0;
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m_axi_awlen[7:0] <= 8'd0;
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m_axi_awsize[2:0] <= 3'd0;
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awvalid_b <= 1'b0;
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awaddr_b <= 'd0;
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awlen_b[7:0] <= 'd0;
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awsize_b[2:0] <= 'd0;
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end
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else
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begin
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if( ~m_axi_awvalid | aw_go )
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begin
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if( awvalid_b )
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begin
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m_axi_awvalid <= 1'b1;
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m_axi_awaddr[31:0] <= awaddr_b[31:0];
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m_axi_awlen[7:0] <= awlen_b[7:0];
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m_axi_awsize[2:0] <= awsize_b[2:0];
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end
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else
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begin
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m_axi_awvalid <= awvalid_in;
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m_axi_awaddr[31:0] <= rxwr_dstaddr[31:0];
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m_axi_awlen[7:0] <= 8'b0;
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m_axi_awsize[2:0] <= { 1'b0, rxwr_datamode[1:0]};
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end
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end
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if( awvalid_in & m_axi_awvalid & ~aw_go )
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awvalid_b <= 1'b1;
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else if( aw_go )
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awvalid_b <= 1'b0;
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//Pipeline stage
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if( awvalid_in )
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begin
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awaddr_b[31:0] <= rxwr_dstaddr[31:0];
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awlen_b[7:0] <= 8'b0;
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awsize_b[2:0] <= { 1'b0, rxwr_datamode[1:0] };
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end
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end // else: !if(~m_axi_aresetn)
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//#########################################################################
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//Write data alignment circuit
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//#########################################################################
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always @*
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case( rxwr_datamode[1:0] )
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2'b00: wdata_aligned[63:0] = { 8{rxwr_data[7:0]}};
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2'b01: wdata_aligned[63:0] = { 4{rxwr_data[15:0]}};
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2'b10: wdata_aligned[63:0] = { 2{rxwr_data[31:0]}};
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default: wdata_aligned[63:0] = { rxwr_srcaddr[31:0], rxwr_data[31:0]};
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endcase
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always @*
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begin
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case(rxwr_datamode[1:0])
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2'd0: // byte
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case(rxwr_dstaddr[2:0])
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3'd0: wstrb_aligned[7:0] = 8'h01;
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3'd1: wstrb_aligned[7:0] = 8'h02;
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3'd2: wstrb_aligned[7:0] = 8'h04;
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3'd3: wstrb_aligned[7:0] = 8'h08;
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3'd4: wstrb_aligned[7:0] = 8'h10;
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3'd5: wstrb_aligned[7:0] = 8'h20;
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3'd6: wstrb_aligned[7:0] = 8'h40;
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default: wstrb_aligned[7:0] = 8'h80;
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endcase
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2'd1: // 16b hword
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case(rxwr_dstaddr[2:1])
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2'd0: wstrb_aligned[7:0] = 8'h03;
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2'd1: wstrb_aligned[7:0] = 8'h0c;
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2'd2: wstrb_aligned[7:0] = 8'h30;
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default: wstrb_aligned[7:0] = 8'hc0;
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endcase
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2'd2: // 32b word
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if(rxwr_dstaddr[2])
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wstrb_aligned[7:0] = 8'hf0;
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else
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wstrb_aligned[7:0] = 8'h0f;
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2'd3:
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wstrb_aligned[7:0] = 8'hff;
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endcase // case (emwr_datamode[1:0])
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end // always @ *
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//#########################################################################
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//Write data channel
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//#########################################################################
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always @ (posedge m_axi_aclk )
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if(~m_axi_aresetn)
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begin
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m_axi_wvalid <= 1'b0;
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m_axi_wdata[63:0] <= 64'b0;
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m_axi_wstrb[7:0] <= 8'b0;
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m_axi_wlast <= 1'b1; // TODO:bursts!!
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wvalid_b <= 1'b0;
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wdata_b[63:0] <= 64'b0;
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wstrb_b[7:0] <= 8'b0;
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end
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else
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begin
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if( ~m_axi_wvalid | w_go )
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begin
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if( wvalid_b )
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begin
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m_axi_wvalid <= 1'b1;
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m_axi_wdata[63:0] <= wdata_b[63:0];
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m_axi_wstrb[7:0] <= wstrb_b[7:0];
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end
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else
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begin
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m_axi_wvalid <= awvalid_in;
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m_axi_wdata[63:0] <= wdata_aligned[63:0];
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m_axi_wstrb[7:0] <= wstrb_aligned[7:0];
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end
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end // if ( ~axi_wvalid | w_go )
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if( rxwr_access & m_axi_wvalid & ~w_go )
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wvalid_b <= 1'b1;
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else if( w_go )
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wvalid_b <= 1'b0;
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if( awvalid_in )
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begin
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wdata_b[63:0] <= wdata_aligned[63:0];
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wstrb_b[7:0] <= wstrb_aligned[7:0];
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end
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end // else: !if(~m_axi_aresetn)
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//#########################################################################
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//Read request channel
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//#########################################################################
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//1. read request comes in on ar channel
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//2. use src address to match with writes coming back
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//3. Assumes in order returns
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assign readinfo_in[47:0] =
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{
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7'b0,
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rxrd_srcaddr[31:0],//40:9
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rxrd_dstaddr[2:0], //8:6
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rxrd_ctrlmode[3:0],//5:2
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rxrd_datamode[1:0]
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};
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//Rest synchronization
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wire sync_nreset;
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dsync dsync(.dout (sync_nreset),
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.clk (m_axi_aclk),
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.din (m_axi_aresetn)
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);
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//Synchronous FIFO for read transactions
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fifo_sync
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#(
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// parameters
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.AW (5),
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.DW (48))
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fifo_readinfo_i
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(
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// outputs
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.rd_data (readinfo_out[47:0]),
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.rd_empty (),
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.wr_full (readinfo_full),
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// inputs
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.clk (m_axi_aclk),
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.reset (~sync_nreset),
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.wr_data (readinfo_in[47:0]),
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.wr_en (m_axi_arvalid & m_axi_arready),
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.rd_en (m_axi_rready & m_axi_rvalid)
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);
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assign txrr_datamode[1:0] = readinfo_out[1:0];
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assign txrr_ctrlmode[3:0] = readinfo_out[5:2];
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assign txrr_dstaddr[31:0] = readinfo_out[40:9];
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//#########################################################################
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//Read address channel
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//#########################################################################
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assign m_axi_araddr[31:0] = rxrd_dstaddr[31:0];
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assign m_axi_arsize[2:0] = {1'b0, rxrd_datamode[1:0]};
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assign m_axi_arlen[7:0] = 8'd0;
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assign m_axi_arvalid = rxrd_access & ~readinfo_full;
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assign rxrd_wait = readinfo_full | ~m_axi_arready;
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//#########################################################################
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//Read response channel
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//#########################################################################
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assign m_axi_rready = ~txrr_wait; //pass through
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always @( posedge m_axi_aclk )
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if ( ~m_axi_aresetn )
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m_axi_rdata_reg <= 'b0;
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else
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m_axi_rdata_reg <= m_axi_rdata;
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always @( posedge m_axi_aclk )
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if( ~m_axi_aresetn )
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begin
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txrr_data[31:0] <= 32'b0;
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txrr_srcaddr[31:0] <= 32'b0;
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txrr_access_reg <= 1'b0;
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txrr_access <= 1'b0;
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end
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else
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begin
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txrr_access_reg <= m_axi_rready & m_axi_rvalid;
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txrr_access <= txrr_access_reg;//added pipeline stage for data
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// steer read data according to size & host address lsbs
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//all data needs to be right aligned
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//(this is due to the Epiphany right aligning all words)
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case(readinfo_out[1:0])//datamode
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2'd0: // byte read
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case(readinfo_out[8:6])
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3'd0: txrr_data[31:0] <= {24'b0,m_axi_rdata_reg[7:0]};
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3'd1: txrr_data[31:0] <= {24'b0,m_axi_rdata_reg[15:8]};
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3'd2: txrr_data[31:0] <= {24'b0,m_axi_rdata_reg[23:16]};
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3'd3: txrr_data[31:0] <= {24'b0,m_axi_rdata_reg[31:24]};
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3'd4: txrr_data[31:0] <= {24'b0,m_axi_rdata_reg[39:32]};
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3'd5: txrr_data[31:0] <= {24'b0,m_axi_rdata_reg[47:40]};
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3'd6: txrr_data[31:0] <= {24'b0,m_axi_rdata_reg[55:48]};
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default: txrr_data[31:0] <= {24'b0,m_axi_rdata_reg[63:56]};
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endcase
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2'd1: // 16b hword
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case( readinfo_out[8:7] )
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2'd0: txrr_data[31:0] <= {16'b0,m_axi_rdata_reg[15:0]};
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2'd1: txrr_data[31:0] <= {16'b0,m_axi_rdata_reg[31:16]};
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2'd2: txrr_data[31:0] <= {16'b0,m_axi_rdata_reg[47:32]};
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default: txrr_data[31:0] <= {16'b0,m_axi_rdata_reg[63:48]};
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endcase
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2'd2: // 32b word
|
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if( readinfo_out[8] )
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txrr_data[31:0] <= m_axi_rdata_reg[63:32];
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else
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txrr_data[31:0] <= m_axi_rdata_reg[31:0];
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// 64b word already defined by defaults above
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2'd3:
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begin // 64b dword
|
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txrr_data[31:0] <= m_axi_rdata_reg[31:0];
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txrr_srcaddr[31:0] <= m_axi_rdata_reg[63:32];
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end
|
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endcase
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end // else: !if( ~m_axi_aresetn )
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endmodule // emaxi
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// Local Variables:
|
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// verilog-library-directories:("." "../../emesh/hdl" "../../memory/hdl" "../../common/hdl" )
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// End:
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