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23 lines
274 B
Verilog
23 lines
274 B
Verilog
module OBUFTDS (/*AUTOARG*/
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// Outputs
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O, OB,
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// Inputs
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I, T
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);
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parameter IOSTANDARD=0;
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parameter SLEW=0;
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input I;
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input T;
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output O;
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output OB;
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assign O = T ? 1'bz : I;
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assign OB = T ? 1'bz : ~I;
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endmodule // OBUFTDS
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