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28 lines
479 B
Verilog
28 lines
479 B
Verilog
module fifo_103x32(/*AUTOARG*/
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// Outputs
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dout, empty, full, prog_full,
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// Inputs
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din, rd_clk, rd_en, rst, wr_clk, wr_en
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);
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input [102:0] din;
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output [102:0] dout;
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output empty;
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output full;
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output prog_full;
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input rd_clk;
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input rd_en;
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input rst;
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input wr_clk;
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input wr_en;
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assign dout = 103'b0;
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assign empty = 1'b0;
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assign full = 1'b0;
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assign prog_full = 1'b0;
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endmodule // fifo_103x32
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