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551 lines
24 KiB
Verilog
551 lines
24 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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// Inputs
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clk, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2;
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parameter IDW = 12;
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parameter S_IDW = 12;
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parameter M_IDW = 6;
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parameter PW = 104;
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parameter N = 1;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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/*AUTOINPUT*/
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//floating wires
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wire elink0_cclk_n; // From elink0 of elink.v
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wire elink0_cclk_p; // From elink0 of elink.v
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wire elink0_chip_resetb; // From elink0 of elink.v
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wire [11:0] elink0_chipid; // From elink0 of elink.v
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wire elink0_mailbox_full; // From elink0 of elink.v
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wire elink0_mailbox_not_empty;// From elink0 of elink.v
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wire elink0_timeout; // From elink0 of elink.v
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wire elink1_cclk_n; // From elink1 of elink.v
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wire elink1_cclk_p; // From elink1 of elink.v
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wire elink1_chip_resetb; // From elink1 of elink.v
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wire [11:0] elink1_chipid; // From elink1 of elink.v
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wire elink1_mailbox_full; // From elink1 of elink.v
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wire elink1_mailbox_not_empty;// From elink1 of elink.v
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wire elink1_rxrd_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxrd_packet; // From elink1 of elink.v
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wire elink1_rxrr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxrr_packet; // From elink1 of elink.v
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wire elink1_rxwr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxwr_packet; // From elink1 of elink.v
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wire elink1_timeout; // From elink1 of elink.v
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wire elink1_txrd_wait; // From elink1 of elink.v
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wire elink1_txrr_access; // From emem of ememory.v
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wire [PW-1:0] elink1_txrr_packet; // From emem of ememory.v
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wire elink1_txrr_wait; // From elink1 of elink.v
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wire elink1_txwr_wait; // From elink1 of elink.v
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//memory wires
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wire emem_access;
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wire [PW-1:0] emem_packet;
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wire elink1_rxrd_wait;
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wire elink1_rxwr_wait;
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// Beginning of automatic outputs (from unused autoinst outputs)
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire elink0_chip_nreset; // From elink0 of axi_elink.v
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wire [31:0] elink0_m_axi_araddr; // From elink0 of axi_elink.v
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wire [1:0] elink0_m_axi_arburst; // From elink0 of axi_elink.v
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wire [3:0] elink0_m_axi_arcache; // From elink0 of axi_elink.v
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wire [M_IDW-1:0] elink0_m_axi_arid; // From elink0 of axi_elink.v
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wire [7:0] elink0_m_axi_arlen; // From elink0 of axi_elink.v
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wire [1:0] elink0_m_axi_arlock; // From elink0 of axi_elink.v
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wire [2:0] elink0_m_axi_arprot; // From elink0 of axi_elink.v
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wire [3:0] elink0_m_axi_arqos; // From elink0 of axi_elink.v
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wire [2:0] elink0_m_axi_arsize; // From elink0 of axi_elink.v
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wire elink0_m_axi_arvalid; // From elink0 of axi_elink.v
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wire [31:0] elink0_m_axi_awaddr; // From elink0 of axi_elink.v
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wire [1:0] elink0_m_axi_awburst; // From elink0 of axi_elink.v
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wire [3:0] elink0_m_axi_awcache; // From elink0 of axi_elink.v
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wire [M_IDW-1:0] elink0_m_axi_awid; // From elink0 of axi_elink.v
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wire [7:0] elink0_m_axi_awlen; // From elink0 of axi_elink.v
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wire [1:0] elink0_m_axi_awlock; // From elink0 of axi_elink.v
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wire [2:0] elink0_m_axi_awprot; // From elink0 of axi_elink.v
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wire [3:0] elink0_m_axi_awqos; // From elink0 of axi_elink.v
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wire [2:0] elink0_m_axi_awsize; // From elink0 of axi_elink.v
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wire elink0_m_axi_awvalid; // From elink0 of axi_elink.v
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wire elink0_m_axi_bready; // From elink0 of axi_elink.v
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wire elink0_m_axi_rready; // From elink0 of axi_elink.v
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wire [63:0] elink0_m_axi_wdata; // From elink0 of axi_elink.v
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wire [M_IDW-1:0] elink0_m_axi_wid; // From elink0 of axi_elink.v
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wire elink0_m_axi_wlast; // From elink0 of axi_elink.v
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wire [7:0] elink0_m_axi_wstrb; // From elink0 of axi_elink.v
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wire elink0_m_axi_wvalid; // From elink0 of axi_elink.v
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wire elink0_rxo_rd_wait_n; // From elink0 of axi_elink.v
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wire elink0_rxo_rd_wait_p; // From elink0 of axi_elink.v
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wire elink0_rxo_wr_wait_n; // From elink0 of axi_elink.v
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wire elink0_rxo_wr_wait_p; // From elink0 of axi_elink.v
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wire elink0_rxrr_access; // From emaxi of emaxi.v
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wire [PW-1:0] elink0_rxrr_packet; // From emaxi of emaxi.v
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wire [7:0] elink0_txo_data_n; // From elink0 of axi_elink.v
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wire [7:0] elink0_txo_data_p; // From elink0 of axi_elink.v
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wire elink0_txo_frame_n; // From elink0 of axi_elink.v
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wire elink0_txo_frame_p; // From elink0 of axi_elink.v
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wire elink0_txo_lclk_n; // From elink0 of axi_elink.v
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wire elink0_txo_lclk_p; // From elink0 of axi_elink.v
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wire elink0_txrd_access; // From emesh_if of emesh_if.v
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wire [PW-1:0] elink0_txrd_packet; // From emesh_if of emesh_if.v
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wire elink0_txrd_wait; // From emaxi of emaxi.v
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wire elink0_txwr_access; // From emesh_if of emesh_if.v
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wire [PW-1:0] elink0_txwr_packet; // From emesh_if of emesh_if.v
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wire elink0_txwr_wait; // From emaxi of emaxi.v
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wire elink1_chip_nreset; // From elink1 of elink.v
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wire elink1_elink_active; // From elink1 of elink.v
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wire elink1_rxo_rd_wait_n; // From elink1 of elink.v
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wire elink1_rxo_rd_wait_p; // From elink1 of elink.v
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wire elink1_rxo_wr_wait_n; // From elink1 of elink.v
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wire elink1_rxo_wr_wait_p; // From elink1 of elink.v
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wire [7:0] elink1_txo_data_n; // From elink1 of elink.v
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wire [7:0] elink1_txo_data_p; // From elink1 of elink.v
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wire elink1_txo_frame_n; // From elink1 of elink.v
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wire elink1_txo_frame_p; // From elink1 of elink.v
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wire elink1_txo_lclk_n; // From elink1 of elink.v
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wire elink1_txo_lclk_p; // From elink1 of elink.v
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wire [31:0] m_axi_araddr; // From emaxi of emaxi.v
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wire [1:0] m_axi_arburst; // From emaxi of emaxi.v
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wire [3:0] m_axi_arcache; // From emaxi of emaxi.v
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wire [M_IDW-1:0] m_axi_arid; // From emaxi of emaxi.v
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wire [7:0] m_axi_arlen; // From emaxi of emaxi.v
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wire [1:0] m_axi_arlock; // From emaxi of emaxi.v
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wire [2:0] m_axi_arprot; // From emaxi of emaxi.v
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wire [3:0] m_axi_arqos; // From emaxi of emaxi.v
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wire m_axi_arready; // From elink0 of axi_elink.v
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wire [2:0] m_axi_arsize; // From emaxi of emaxi.v
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wire m_axi_arvalid; // From emaxi of emaxi.v
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wire [31:0] m_axi_awaddr; // From emaxi of emaxi.v
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wire [1:0] m_axi_awburst; // From emaxi of emaxi.v
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wire [3:0] m_axi_awcache; // From emaxi of emaxi.v
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wire [M_IDW-1:0] m_axi_awid; // From emaxi of emaxi.v
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wire [7:0] m_axi_awlen; // From emaxi of emaxi.v
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wire [1:0] m_axi_awlock; // From emaxi of emaxi.v
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wire [2:0] m_axi_awprot; // From emaxi of emaxi.v
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wire [3:0] m_axi_awqos; // From emaxi of emaxi.v
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wire m_axi_awready; // From elink0 of axi_elink.v
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wire [2:0] m_axi_awsize; // From emaxi of emaxi.v
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wire m_axi_awvalid; // From emaxi of emaxi.v
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wire [S_IDW-1:0] m_axi_bid; // From elink0 of axi_elink.v
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wire m_axi_bready; // From emaxi of emaxi.v
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wire [1:0] m_axi_bresp; // From elink0 of axi_elink.v
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wire m_axi_bvalid; // From elink0 of axi_elink.v
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wire [31:0] m_axi_rdata; // From elink0 of axi_elink.v
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wire [S_IDW-1:0] m_axi_rid; // From elink0 of axi_elink.v
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wire m_axi_rlast; // From elink0 of axi_elink.v
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wire m_axi_rready; // From emaxi of emaxi.v
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wire [1:0] m_axi_rresp; // From elink0 of axi_elink.v
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wire m_axi_rvalid; // From elink0 of axi_elink.v
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wire [63:0] m_axi_wdata; // From emaxi of emaxi.v
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wire [M_IDW-1:0] m_axi_wid; // From emaxi of emaxi.v
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wire m_axi_wlast; // From emaxi of emaxi.v
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wire m_axi_wready; // From elink0 of axi_elink.v
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wire [7:0] m_axi_wstrb; // From emaxi of emaxi.v
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wire m_axi_wvalid; // From emaxi of emaxi.v
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// End of automatics
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//######################################################################
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//EMESH INTERFACE
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//######################################################################
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/*emesh_if AUTO_TEMPLATE (//Stimulus
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.e2c_emesh_\(.*\)_in(\1_in[]),
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.e2c_emesh_\(.*\)_out(\1_out[]),
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//Response
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.c2e_emesh_\(.*\)_out(\1_out[]),
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.c2e_emesh_\(.*\)_in(\1_in[]),
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.c2e_cmesh_\(.*\)_in(elink0_rxrr_\1[]),
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//Link side transaction outgoing
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.e2c_cmesh_\(.*\)_out(elink0_txwr_\1[]),
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.e2c_cmesh_wait_in(elink0_txwr_wait),
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.e2c_rmesh_\(.*\)_out(elink0_txrd_\1[]),
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.e2c_rmesh_wait_in(elink0_txrd_wait),
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.c2e_\(.*\)_wait_out(),
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);
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*/
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emesh_if #(.PW(PW)) emesh_if (.c2e_rmesh_access_in(1'b0),
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.c2e_rmesh_packet_in({(PW){1'b0}}),
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.c2e_xmesh_access_in(1'b0),
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.c2e_xmesh_packet_in({(PW){1'b0}}),
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.e2c_xmesh_wait_in(1'b0),
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.e2c_xmesh_access_out(),
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.e2c_xmesh_packet_out(),
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/*AUTOINST*/
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// Outputs
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.c2e_cmesh_wait_out (), // Templated
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.e2c_cmesh_access_out (elink0_txwr_access), // Templated
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.e2c_cmesh_packet_out (elink0_txwr_packet[PW-1:0]), // Templated
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.c2e_rmesh_wait_out (), // Templated
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.e2c_rmesh_access_out (elink0_txrd_access), // Templated
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.e2c_rmesh_packet_out (elink0_txrd_packet[PW-1:0]), // Templated
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.c2e_xmesh_wait_out (), // Templated
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.e2c_emesh_wait_out (wait_out), // Templated
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.c2e_emesh_access_out (access_out), // Templated
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.c2e_emesh_packet_out (packet_out[PW-1:0]), // Templated
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// Inputs
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.c2e_cmesh_access_in (elink0_rxrr_access), // Templated
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.c2e_cmesh_packet_in (elink0_rxrr_packet[PW-1:0]), // Templated
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.e2c_cmesh_wait_in (elink0_txwr_wait), // Templated
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.e2c_rmesh_wait_in (elink0_txrd_wait), // Templated
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.e2c_emesh_access_in (access_in), // Templated
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.e2c_emesh_packet_in (packet_in[PW-1:0]), // Templated
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.c2e_emesh_wait_in (wait_in)); // Templated
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//######################################################################
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//AXI MASTER
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//######################################################################
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/*emaxi AUTO_TEMPLATE (//Stimulus
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.rxwr_access (elink0_txwr_access),
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.rxwr_packet (elink0_txwr_packet[PW-1:0]),
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.rxwr_wait (elink0_txwr_wait),
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.rxrd_access (elink0_txrd_access),
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.rxrd_packet (elink0_txrd_packet[PW-1:0]),
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.rxrd_wait (elink0_txrd_wait),
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//outputs (read response back to monitor)
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.txrr_access (elink0_rxrr_access),
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.txrr_packet (elink0_rxrr_packet[PW-1:0]),
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.txrr_wait (1'b0),
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);
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*/
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emaxi #(.M_IDW(M_IDW))
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emaxi (.m_axi_aclk (clk),
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.m_axi_aresetn (nreset),
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.m_axi_rdata ({m_axi_rdata[31:0],m_axi_rdata[31:0]}),
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/*AUTOINST*/
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// Outputs
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.rxwr_wait (elink0_txwr_wait), // Templated
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.rxrd_wait (elink0_txrd_wait), // Templated
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.txrr_access (elink0_rxrr_access), // Templated
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.txrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
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.m_axi_awid (m_axi_awid[M_IDW-1:0]),
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.m_axi_awaddr (m_axi_awaddr[31:0]),
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.m_axi_awlen (m_axi_awlen[7:0]),
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.m_axi_awsize (m_axi_awsize[2:0]),
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.m_axi_awburst (m_axi_awburst[1:0]),
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.m_axi_awlock (m_axi_awlock[1:0]),
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.m_axi_awcache (m_axi_awcache[3:0]),
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.m_axi_awprot (m_axi_awprot[2:0]),
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.m_axi_awqos (m_axi_awqos[3:0]),
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.m_axi_awvalid (m_axi_awvalid),
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.m_axi_wid (m_axi_wid[M_IDW-1:0]),
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.m_axi_wdata (m_axi_wdata[63:0]),
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.m_axi_wstrb (m_axi_wstrb[7:0]),
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.m_axi_wlast (m_axi_wlast),
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.m_axi_wvalid (m_axi_wvalid),
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.m_axi_bready (m_axi_bready),
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.m_axi_arid (m_axi_arid[M_IDW-1:0]),
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.m_axi_araddr (m_axi_araddr[31:0]),
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.m_axi_arlen (m_axi_arlen[7:0]),
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.m_axi_arsize (m_axi_arsize[2:0]),
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.m_axi_arburst (m_axi_arburst[1:0]),
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.m_axi_arlock (m_axi_arlock[1:0]),
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.m_axi_arcache (m_axi_arcache[3:0]),
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.m_axi_arprot (m_axi_arprot[2:0]),
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.m_axi_arqos (m_axi_arqos[3:0]),
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.m_axi_arvalid (m_axi_arvalid),
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.m_axi_rready (m_axi_rready),
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// Inputs
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.rxwr_access (elink0_txwr_access), // Templated
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.rxwr_packet (elink0_txwr_packet[PW-1:0]), // Templated
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.rxrd_access (elink0_txrd_access), // Templated
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.rxrd_packet (elink0_txrd_packet[PW-1:0]), // Templated
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.txrr_wait (1'b0), // Templated
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.m_axi_awready (m_axi_awready),
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.m_axi_wready (m_axi_wready),
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.m_axi_bid (m_axi_bid[M_IDW-1:0]),
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.m_axi_bresp (m_axi_bresp[1:0]),
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.m_axi_bvalid (m_axi_bvalid),
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.m_axi_arready (m_axi_arready),
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.m_axi_rid (m_axi_rid[M_IDW-1:0]),
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.m_axi_rresp (m_axi_rresp[1:0]),
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.m_axi_rlast (m_axi_rlast),
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.m_axi_rvalid (m_axi_rvalid));
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//######################################################################
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//1ST ELINK
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//######################################################################
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/*axi_elink AUTO_TEMPLATE (
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// Outputs
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.sys_clk (clk),
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.rxi_\(.*\) (elink1_txo_\1[]),
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.txi_\(.*\) (elink1_rxo_\1[]),
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.s_\(.*\) (m_\1[]),
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.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
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);
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*/
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defparam elink0.ID = 12'h810;
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defparam elink0.ETYPE = 0;
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axi_elink elink0 (.s_axi_aresetn (nreset),
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.sys_nreset (nreset),
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.elink_active (dut_active),
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.m_axi_aresetn (1'b1),
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.m_axi_awready (1'b0),
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.m_axi_wready (1'b0),
|
|
.m_axi_bvalid (1'b0),
|
|
.m_axi_arready (1'b0),
|
|
.m_axi_rlast (1'b0),
|
|
.m_axi_rvalid (1'b0),
|
|
.m_axi_bid (6'b0),
|
|
.m_axi_bresp (2'b0),
|
|
.m_axi_rid (6'b0),
|
|
.m_axi_rdata (64'b0),
|
|
.m_axi_rresp (2'b0),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
|
|
.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
|
|
.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
|
|
.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
|
|
.txo_lclk_p (elink0_txo_lclk_p), // Templated
|
|
.txo_lclk_n (elink0_txo_lclk_n), // Templated
|
|
.txo_frame_p (elink0_txo_frame_p), // Templated
|
|
.txo_frame_n (elink0_txo_frame_n), // Templated
|
|
.txo_data_p (elink0_txo_data_p[7:0]), // Templated
|
|
.txo_data_n (elink0_txo_data_n[7:0]), // Templated
|
|
.chipid (elink0_chipid[11:0]), // Templated
|
|
.chip_nreset (elink0_chip_nreset), // Templated
|
|
.cclk_p (elink0_cclk_p), // Templated
|
|
.cclk_n (elink0_cclk_n), // Templated
|
|
.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
|
|
.mailbox_full (elink0_mailbox_full), // Templated
|
|
.m_axi_awid (elink0_m_axi_awid[M_IDW-1:0]), // Templated
|
|
.m_axi_awaddr (elink0_m_axi_awaddr[31:0]), // Templated
|
|
.m_axi_awlen (elink0_m_axi_awlen[7:0]), // Templated
|
|
.m_axi_awsize (elink0_m_axi_awsize[2:0]), // Templated
|
|
.m_axi_awburst (elink0_m_axi_awburst[1:0]), // Templated
|
|
.m_axi_awlock (elink0_m_axi_awlock[1:0]), // Templated
|
|
.m_axi_awcache (elink0_m_axi_awcache[3:0]), // Templated
|
|
.m_axi_awprot (elink0_m_axi_awprot[2:0]), // Templated
|
|
.m_axi_awqos (elink0_m_axi_awqos[3:0]), // Templated
|
|
.m_axi_awvalid (elink0_m_axi_awvalid), // Templated
|
|
.m_axi_wid (elink0_m_axi_wid[M_IDW-1:0]), // Templated
|
|
.m_axi_wdata (elink0_m_axi_wdata[63:0]), // Templated
|
|
.m_axi_wstrb (elink0_m_axi_wstrb[7:0]), // Templated
|
|
.m_axi_wlast (elink0_m_axi_wlast), // Templated
|
|
.m_axi_wvalid (elink0_m_axi_wvalid), // Templated
|
|
.m_axi_bready (elink0_m_axi_bready), // Templated
|
|
.m_axi_arid (elink0_m_axi_arid[M_IDW-1:0]), // Templated
|
|
.m_axi_araddr (elink0_m_axi_araddr[31:0]), // Templated
|
|
.m_axi_arlen (elink0_m_axi_arlen[7:0]), // Templated
|
|
.m_axi_arsize (elink0_m_axi_arsize[2:0]), // Templated
|
|
.m_axi_arburst (elink0_m_axi_arburst[1:0]), // Templated
|
|
.m_axi_arlock (elink0_m_axi_arlock[1:0]), // Templated
|
|
.m_axi_arcache (elink0_m_axi_arcache[3:0]), // Templated
|
|
.m_axi_arprot (elink0_m_axi_arprot[2:0]), // Templated
|
|
.m_axi_arqos (elink0_m_axi_arqos[3:0]), // Templated
|
|
.m_axi_arvalid (elink0_m_axi_arvalid), // Templated
|
|
.m_axi_rready (elink0_m_axi_rready), // Templated
|
|
.s_axi_arready (m_axi_arready), // Templated
|
|
.s_axi_awready (m_axi_awready), // Templated
|
|
.s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated
|
|
.s_axi_bresp (m_axi_bresp[1:0]), // Templated
|
|
.s_axi_bvalid (m_axi_bvalid), // Templated
|
|
.s_axi_rid (m_axi_rid[S_IDW-1:0]), // Templated
|
|
.s_axi_rdata (m_axi_rdata[31:0]), // Templated
|
|
.s_axi_rlast (m_axi_rlast), // Templated
|
|
.s_axi_rresp (m_axi_rresp[1:0]), // Templated
|
|
.s_axi_rvalid (m_axi_rvalid), // Templated
|
|
.s_axi_wready (m_axi_wready), // Templated
|
|
.timeout (elink0_timeout), // Templated
|
|
// Inputs
|
|
.sys_clk (clk), // Templated
|
|
.rxi_lclk_p (elink1_txo_lclk_p), // Templated
|
|
.rxi_lclk_n (elink1_txo_lclk_n), // Templated
|
|
.rxi_frame_p (elink1_txo_frame_p), // Templated
|
|
.rxi_frame_n (elink1_txo_frame_n), // Templated
|
|
.rxi_data_p (elink1_txo_data_p[7:0]), // Templated
|
|
.rxi_data_n (elink1_txo_data_n[7:0]), // Templated
|
|
.txi_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
|
|
.txi_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
|
|
.txi_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
|
|
.txi_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
|
|
.s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated
|
|
.s_axi_araddr (m_axi_araddr[31:0]), // Templated
|
|
.s_axi_arburst (m_axi_arburst[1:0]), // Templated
|
|
.s_axi_arcache (m_axi_arcache[3:0]), // Templated
|
|
.s_axi_arlock (m_axi_arlock[1:0]), // Templated
|
|
.s_axi_arlen (m_axi_arlen[7:0]), // Templated
|
|
.s_axi_arprot (m_axi_arprot[2:0]), // Templated
|
|
.s_axi_arqos (m_axi_arqos[3:0]), // Templated
|
|
.s_axi_arsize (m_axi_arsize[2:0]), // Templated
|
|
.s_axi_arvalid (m_axi_arvalid), // Templated
|
|
.s_axi_awid (m_axi_awid[S_IDW-1:0]), // Templated
|
|
.s_axi_awaddr (m_axi_awaddr[31:0]), // Templated
|
|
.s_axi_awburst (m_axi_awburst[1:0]), // Templated
|
|
.s_axi_awcache (m_axi_awcache[3:0]), // Templated
|
|
.s_axi_awlock (m_axi_awlock[1:0]), // Templated
|
|
.s_axi_awlen (m_axi_awlen[7:0]), // Templated
|
|
.s_axi_awprot (m_axi_awprot[2:0]), // Templated
|
|
.s_axi_awqos (m_axi_awqos[3:0]), // Templated
|
|
.s_axi_awsize (m_axi_awsize[2:0]), // Templated
|
|
.s_axi_awvalid (m_axi_awvalid), // Templated
|
|
.s_axi_bready (m_axi_bready), // Templated
|
|
.s_axi_rready (m_axi_rready), // Templated
|
|
.s_axi_wid (m_axi_wid[S_IDW-1:0]), // Templated
|
|
.s_axi_wdata (m_axi_wdata[31:0]), // Templated
|
|
.s_axi_wlast (m_axi_wlast), // Templated
|
|
.s_axi_wstrb (m_axi_wstrb[3:0]), // Templated
|
|
.s_axi_wvalid (m_axi_wvalid)); // Templated
|
|
|
|
|
|
//######################################################################
|
|
//2ND ELINK (WITH EPIPHANY MEMORY)
|
|
//######################################################################
|
|
/*elink AUTO_TEMPLATE (
|
|
// Outputs
|
|
.sys_clk (clk),
|
|
.sys_nreset (nreset),
|
|
.rxi_\(.*\) (elink0_txo_\1[]),
|
|
.txi_\(.*\) (elink0_rxo_\1[]),
|
|
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
|
|
|
|
);
|
|
*/
|
|
//No read/write from elink1 (for now)
|
|
assign elink1_txrd_access = 1'b0;
|
|
assign elink1_txrd_packet = 'b0;
|
|
assign elink1_txwr_access = 1'b0;
|
|
assign elink1_txwr_packet = 'b0;
|
|
assign elink1_rxrr_wait = 1'b0;
|
|
|
|
defparam elink1.ID = 12'h820;
|
|
defparam elink1.ETYPE = 0;
|
|
|
|
elink elink1 (.rxrr_wait (1'b0),
|
|
.txwr_access (1'b0),
|
|
.txwr_packet ({(PW){1'b0}}),
|
|
.txrd_access (1'b0),
|
|
.txrd_packet ({(PW){1'b0}}),
|
|
.txrr_access (elink1_txrr_access),
|
|
.txrr_packet (elink1_txrr_packet[PW-1:0]),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.elink_active (elink1_elink_active), // Templated
|
|
.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
|
|
.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
|
|
.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
|
|
.rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
|
|
.txo_lclk_p (elink1_txo_lclk_p), // Templated
|
|
.txo_lclk_n (elink1_txo_lclk_n), // Templated
|
|
.txo_frame_p (elink1_txo_frame_p), // Templated
|
|
.txo_frame_n (elink1_txo_frame_n), // Templated
|
|
.txo_data_p (elink1_txo_data_p[7:0]), // Templated
|
|
.txo_data_n (elink1_txo_data_n[7:0]), // Templated
|
|
.chipid (elink1_chipid[11:0]), // Templated
|
|
.cclk_p (elink1_cclk_p), // Templated
|
|
.cclk_n (elink1_cclk_n), // Templated
|
|
.chip_nreset (elink1_chip_nreset), // Templated
|
|
.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
|
|
.mailbox_full (elink1_mailbox_full), // Templated
|
|
.timeout (elink1_timeout), // Templated
|
|
.rxwr_access (elink1_rxwr_access), // Templated
|
|
.rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated
|
|
.rxrd_access (elink1_rxrd_access), // Templated
|
|
.rxrd_packet (elink1_rxrd_packet[PW-1:0]), // Templated
|
|
.rxrr_access (elink1_rxrr_access), // Templated
|
|
.rxrr_packet (elink1_rxrr_packet[PW-1:0]), // Templated
|
|
.txwr_wait (elink1_txwr_wait), // Templated
|
|
.txrd_wait (elink1_txrd_wait), // Templated
|
|
.txrr_wait (elink1_txrr_wait), // Templated
|
|
// Inputs
|
|
.sys_nreset (nreset), // Templated
|
|
.sys_clk (clk), // Templated
|
|
.rxi_lclk_p (elink0_txo_lclk_p), // Templated
|
|
.rxi_lclk_n (elink0_txo_lclk_n), // Templated
|
|
.rxi_frame_p (elink0_txo_frame_p), // Templated
|
|
.rxi_frame_n (elink0_txo_frame_n), // Templated
|
|
.rxi_data_p (elink0_txo_data_p[7:0]), // Templated
|
|
.rxi_data_n (elink0_txo_data_n[7:0]), // Templated
|
|
.txi_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
|
|
.txi_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
|
|
.txi_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
|
|
.txi_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
|
|
.rxwr_wait (elink1_rxwr_wait), // Templated
|
|
.rxrd_wait (elink1_rxrd_wait)); // Templated
|
|
|
|
|
|
//"Arbitration" between read/write transaction
|
|
assign emem_access = elink1_rxwr_access | elink1_rxrd_access;
|
|
|
|
assign emem_packet[PW-1:0] = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
|
|
elink1_rxrd_packet[PW-1:0];
|
|
|
|
assign elink1_rxrd_wait = emem_wait | elink1_rxwr_access;
|
|
assign elink1_rxwr_wait = 1'b0;//TODO: elink1_random_wait
|
|
|
|
/*ememory AUTO_TEMPLATE (
|
|
// Outputs
|
|
.\(.*\)_out (elink1_txrr_\1[]),
|
|
.\(.*\)_in (emem_\1[]),
|
|
.wait_out (emem_wait),
|
|
.reset (~nreset),
|
|
);
|
|
*/
|
|
|
|
ememory emem (.wait_in (elink1_txrr_wait),//pushback on reads
|
|
.clk (clk),
|
|
.wait_out (emem_wait),
|
|
.coreid (12'h0),
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.access_out (elink1_txrr_access), // Templated
|
|
.packet_out (elink1_txrr_packet[PW-1:0]), // Templated
|
|
// Inputs
|
|
.nreset (nreset),
|
|
.access_in (emem_access), // Templated
|
|
.packet_in (emem_packet[PW-1:0])); // Templated
|
|
|
|
|
|
endmodule // dv_elink
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl")
|
|
// End:
|
|
|
|
|