mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
18084bf63f
-adding target parameter to fifo -fixing rx protocol bugs -adding defaults to register file, usually these should be set to zero and -don't clock gate the DDR TX, just causes output to toggle like clock, BAD! -fixed status register sticky bug -adding autoincrement feature in amode -fixing dut file for new "mio" subsystem -**emesh packet now goes through in loopback!!!**
121 lines
3.6 KiB
Verilog
121 lines
3.6 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, clkout, wait_out, access_out, packet_out,
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// Inputs
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clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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parameter N = 1;
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parameter AW = 32; // address width
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parameter NMIO = 8; // IO data width
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localparam PW = 2*AW + 40; // standard packet
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localparam CW = $clog2(2*PW/NMIO);// transfer count width
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//clock, reset
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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output clkout;
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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//wires
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wire reg_access_in;
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wire [PW-1:0] reg_packet_in;
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wire [7:0] datasize;
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wire [3:0] divcfg;
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wire [7:0] clkdiv;
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/*AUTOINPUT*/
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire reg_access_out; // From mio of mio.v
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wire [PW-1:0] reg_packet_out; // From mio of mio.v
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wire reg_wait_out; // From mio of mio.v
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wire rx_wait; // From mio of mio.v
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wire tx_access; // From mio of mio.v
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wire tx_clk; // From mio of mio.v
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wire [NMIO-1:0] tx_packet; // From mio of mio.v
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// End of automatics
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assign dut_active = 1'b1;
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assign datasize[CW-1:0] = PW/(2*NMIO);
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assign divcfg = 4'b1;
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assign clkout = clk1;
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assign reg_access_in = 'b0;
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assign reg_packet_in = 'b0;
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assign reg_wait_in = wait_in;
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//########################################
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//# DUT: MIO IN LOOPBACK
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//########################################
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/*mio AUTO_TEMPLATE (
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.io_clk (io_clk),
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.clk (clk1),
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.rx_clk (tx_clk),
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.rx_access (tx_access),
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.rx_packet (tx_packet[NMIO-1:0]),
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.tx_packet (tx_packet[NMIO-1:0]),
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.tx_wait (rx_wait),
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.reg_access_in (reg_access_in),
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.reg_packet_in (reg_packet_in[PW-1:0]),
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.reg_wait_in (wait_in),
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);
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*/
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mio mio (/*AUTOINST*/
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// Outputs
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.tx_clk (tx_clk),
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.tx_access (tx_access),
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.tx_packet (tx_packet[NMIO-1:0]), // Templated
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.rx_wait (rx_wait),
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.wait_out (wait_out),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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.reg_wait_out (reg_wait_out),
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.reg_access_out (reg_access_out),
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.reg_packet_out (reg_packet_out[PW-1:0]),
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// Inputs
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.clk (clk1), // Templated
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.nreset (nreset),
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.tx_wait (rx_wait), // Templated
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.rx_clk (tx_clk), // Templated
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.rx_access (tx_access), // Templated
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.rx_packet (tx_packet[NMIO-1:0]), // Templated
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]),
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.wait_in (wait_in),
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.reg_access_in (reg_access_in), // Templated
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.reg_packet_in (reg_packet_in[PW-1:0]), // Templated
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.reg_wait_in (wait_in)); // Templated
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endmodule // dv_elink
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../common/hdl" "../../emesh/dv" "../../emesh/hdl")
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// End:
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