mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
18084bf63f
-adding target parameter to fifo -fixing rx protocol bugs -adding defaults to register file, usually these should be set to zero and -don't clock gate the DDR TX, just causes output to toggle like clock, BAD! -fixed status register sticky bug -adding autoincrement feature in amode -fixing dut file for new "mio" subsystem -**emesh packet now goes through in loopback!!!**
106 lines
2.9 KiB
Verilog
106 lines
2.9 KiB
Verilog
module mio_dp (/*AUTOARG*/
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// Outputs
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tx_full, tx_prog_full, tx_empty, rx_full, rx_prog_full, rx_empty,
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tx_access, tx_packet, rx_wait, wait_out, access_out, packet_out,
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// Inputs
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clk, io_clk, nreset, datasize, ddr_mode, lsbfirst, tx_en, rx_en,
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tx_wait, rx_clk, rx_access, rx_packet, access_in, packet_in,
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wait_in
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);
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//#####################################################################
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//# INTERFACE
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//#####################################################################
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//parameters
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parameter PW = 104; // data width (core)
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parameter N = 8; // Mini IO width
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parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
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// reset, clk, config
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input clk; // main core clock
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input io_clk; // clock for TX
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input nreset; // async active low reset
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input [7:0] datasize; // size of data transmitted
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input ddr_mode; // dual data rate mode
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input lsbfirst; // send data lsbfirst
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input tx_en; // enable transmit
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input rx_en; // enable receive
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// status
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output tx_full;
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output tx_prog_full;
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output tx_empty;
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output rx_full;
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output rx_prog_full;
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output rx_empty;
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// tx interface
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output tx_access; // access signal for IO
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output [N-1:0] tx_packet; // packet for IO
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input tx_wait; // pushback from IO
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// rx interface
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input rx_clk; // rx clock
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input rx_access; // rx access
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input [N-1:0] rx_packet; // rx packet
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output rx_wait; // pushback from IO
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// core interface
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input access_in; // fifo data valid
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input [PW-1:0] packet_in; // fifo packet
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output wait_out; // wait pushback for fifo
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output access_out; // fifo data valid
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output [PW-1:0] packet_out; // fifo packet
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input wait_in; // wait pushback for fifo
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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mtx #(.N(N),
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.PW(PW))
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mtx (/*AUTOINST*/
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// Outputs
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.wait_out (wait_out),
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.tx_access (tx_access),
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.tx_packet (tx_packet[N-1:0]),
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// Inputs
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.clk (clk),
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.io_clk (io_clk),
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.nreset (nreset),
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.tx_en (tx_en),
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.datasize (datasize[7:0]),
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.ddr_mode (ddr_mode),
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.lsbfirst (lsbfirst),
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]),
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.tx_wait (tx_wait));
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mrx #(.N(N),
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.PW(PW))
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mrx (/*AUTOINST*/
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// Outputs
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.rx_empty (rx_empty),
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.rx_full (rx_full),
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.rx_prog_full (rx_prog_full),
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.rx_wait (rx_wait),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.datasize (datasize[7:0]),
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.ddr_mode (ddr_mode),
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.lsbfirst (lsbfirst),
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.rx_clk (rx_clk),
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.rx_access (rx_access),
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.rx_packet (rx_packet[N-1:0]),
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.wait_in (wait_in));
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endmodule // mio_dp
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