Andreas Olofsson 1890657d6d Solved read response bug. MATMUL WORKS!!!! ...

- Turns out I was debugging ghosts for ~1 day today. Everything was working in simulation but nothing works in the FPGA. Since I was only changing small logic stuff, I didn't bother checking the warning messages in Viviado. Turns out for some reason it was throwing away some logic and disconnecting all the important rr signals
- This is where I was making changes, but I still can't figure out what exactly was happening...doesn't make sense. Either there is a bug in icarus or in vivado, this shouldn't happen!

2015-11-25 23:50:29 -05:00

..

axi_elink.v

Bug fix. Adding missing ID parameter.

2015-11-11 13:58:04 -05:00

ecfg_if.v

Filtering register write transactions

2015-11-25 21:56:56 -05:00

elink_cfg.v

Lint fixes for icarus/verilator

2015-11-09 21:57:25 -05:00

elink_constants.v

Link cleanup

2015-11-02 16:10:05 -05:00

elink_regmap.v

Adding debug logic to elink

2015-11-25 21:53:33 -05:00

elink.v

Fixing reset bug

2015-11-10 09:19:45 -05:00

emaxi.v

Solved read response bug. MATMUL WORKS!!!!

2015-11-25 23:50:29 -05:00

erx_arbiter.v

Re-re-fixing the wait on RX

2015-11-15 01:34:20 -05:00

erx_cfg.v

Adding testing/motnirot logic to link

2015-11-25 12:50:02 -05:00

erx_clocks.v

Complete redesign of the TX

2015-11-24 01:12:07 -05:00

erx_core.v

Adding debug logic to elink

2015-11-25 21:53:33 -05:00

erx_fifo.v

Complete redesign of the TX

2015-11-24 01:12:07 -05:00

erx_io.v

Fixing clock transfer speedpath

2015-11-25 21:54:02 -05:00

erx_protocol.v

Bringing access low during wait

2015-11-12 00:58:06 -05:00

erx_remap.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

erx_timer.v

Converting to synchronous reset

2015-05-17 23:00:53 -04:00

erx.v

Various wait cleanups in RX

2015-11-13 16:28:40 -05:00

esaxi.v

Filtering register write transactions

2015-11-25 21:56:56 -05:00

etx_arbiter.v

Filtering register write transactions

2015-11-25 21:56:56 -05:00

etx_cfg.v

Adding debug logic to elink

2015-11-25 21:53:33 -05:00

etx_clocks.v

Complete redesign of the TX

2015-11-24 01:12:07 -05:00

etx_core.v

Filtering register write transactions

2015-11-25 21:56:56 -05:00

etx_fifo.v

Cleaning up fifo interface

2015-11-09 13:20:46 -05:00

etx_io.v

Filtering out short wait-low pulses from legacy elink

2015-11-25 21:55:37 -05:00

etx_protocol.v

Adding debug logic to elink

2015-11-25 21:53:33 -05:00

etx_remap.v

Filtering register write transactions

2015-11-25 21:56:56 -05:00

etx.v

Filtering register write transactions

2015-11-25 21:56:56 -05:00