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19e22c38d7
If there is a waitm, we should 1.) Not increment the read pointer 2.) Hold the packet steady until wait signal goes away 3.) Hold access high, keep request intact
141 lines
3.6 KiB
Verilog
141 lines
3.6 KiB
Verilog
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module fifo_async
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(/*AUTOARG*/
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// Outputs
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full, prog_full, dout, empty, valid,
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// Inputs
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reset, wr_clk, rd_clk, wr_en, din, rd_en
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);
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parameter DW = 104;
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parameter AW = 2;
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//##########
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//# RESET/CLOCK
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//##########
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input reset; //asynchronous reset
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input wr_clk; //write clock
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input rd_clk; //read clock
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//##########
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//# FIFO WRITE
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//##########
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input wr_en;
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input [DW-1:0] din;
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output full;
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output prog_full;
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//###########
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//# FIFO READ
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//###########
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input rd_en;
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output [DW-1:0] dout;
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output empty;
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output valid;
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reg valid;
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`ifdef TARGET_CLEAN
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//Wires
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wire [DW/8-1:0] wr_vec;
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wire [AW:0] wr_rd_gray_pointer;
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wire [AW:0] rd_wr_gray_pointer;
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wire [AW:0] wr_gray_pointer;
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wire [AW:0] rd_gray_pointer;
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wire [AW-1:0] rd_addr;
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wire [AW-1:0] wr_addr;
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assign wr_vec[DW/8-1:0] = {(DW/8){wr_en}};
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//Valid data at output
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always @ (posedge rd_clk or posedge reset)
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if(reset)
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valid <=1'b0;
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else
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valid <= rd_en;
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memory_dp #(.DW(DW),.AW(AW)) memory_dp (
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// Outputs
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.rd_data (dout[DW-1:0]),
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// Inputs
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.wr_clk (wr_clk),
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.wr_en (wr_vec[DW/8-1:0]),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_data (din[DW-1:0]),
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.rd_clk (rd_clk),
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.rd_en (1'b1),
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.rd_addr (rd_addr[AW-1:0]));
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//Read State Machine
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fifo_empty_block #(.AW(AW)) fifo_empty_block(
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// Outputs
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.rd_fifo_empty (empty),
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.rd_addr (rd_addr[AW-1:0]),
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.rd_gray_pointer(rd_gray_pointer[AW:0]),
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// Inputs
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.reset (reset),
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.rd_clk (rd_clk),
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.rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]),
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.rd_read (rd_en));
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//Write State Machine
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fifo_full_block #(.AW(AW)) fifo_full_block(
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// Outputs
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.wr_fifo_prog_full(prog_full),
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.wr_fifo_full (full),
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.wr_addr (wr_addr[AW-1:0]),
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.wr_gray_pointer (wr_gray_pointer[AW:0]),
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// Inputs
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.reset (reset),
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.wr_clk (wr_clk),
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.wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]),
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.wr_write (wr_en));
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synchronizer #(.DW(AW+1)) rd2wr_sync (.out (wr_rd_gray_pointer[AW:0]),
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.in (rd_gray_pointer[AW:0]),
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.reset (reset),
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.clk (wr_clk));
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synchronizer #(.DW(AW+1)) wr2rd_sync (.out (rd_wr_gray_pointer[AW:0]),
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.in (wr_gray_pointer[AW:0]),
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.reset (reset),
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.clk (rd_clk));
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`elsif TARGET_XILINX
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//insert generate FIFO
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`endif // `ifdef TARGET_CLEAN
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endmodule // fifo_async
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson, Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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