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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
36 lines
646 B
Verilog
36 lines
646 B
Verilog
module oh_clockgate(/*AUTOARG*/
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// Outputs
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eclk,
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// Inputs
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nrst, clk, en, se
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);
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input nrst;//active low reset
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input clk; //clock input
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input en; //enable
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input se; //scan enable
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output eclk;//enabled clock
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`ifdef CFG_ASIC
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`else
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wire en_sh;
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wire en_sl;
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//Turn on clock if in scan mode or if enabled
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assign en_sl = en | se | ~nrst;
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//making signal stable
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oh_lat0 #(.DW(1)) lat0 (.out_sh (en_sh),
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.in_sl (en_sl),
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.clk (clk)
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);
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assign eclk = clk & en_sh;
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`endif
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endmodule // clock_gater
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