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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
52 lines
1.1 KiB
Verilog
52 lines
1.1 KiB
Verilog
//CSA9:2 Compressor
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module oh_csa92 (/*AUTOARG*/
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// Outputs
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s, c, c_out0, c_out1, c_out2, c_out3, c_out4, c_out5,
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// Inputs
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in0, in1, in2, in3, in4, in5, in6, in7, in8, c_in0, c_in1, c_in2,
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c_in3, c_in4, c_in5
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);
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input in0;
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input in1;
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input in2;
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input in3;
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input in4;
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input in5;
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input in6;
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input in7;
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input in8;
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input c_in0;
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input c_in1;
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input c_in2;
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input c_in3;
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input c_in4;
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input c_in5;
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output s;
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output c;
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output c_out0;
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output c_out1;
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output c_out2;
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output c_out3;
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output c_out4;
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output c_out5;
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wire s_int0;
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wire s_int1;
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wire s_int2;
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oh_csa32 csa32_0 (.in0(in0),.in1(in1),.in2(in2),.c(c_out0),.s(s_int0));
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oh_csa32 csa32_1 (.in0(in3),.in1(in4),.in2(in5),.c(c_out1),.s(s_int1));
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oh_csa32 csa32_2 (.in0(in6),.in1(in7),.in2(in8),.c(c_out2),.s(s_int2));
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oh_csa62 csa62 (.in0(s_int0), .in1(s_int1), .in2(s_int2),
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.in3(c_in0), .in4(c_in1), .in5(c_in2),
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.c_in0(c_in3), .c_in1(c_in4), .c_in2(c_in5),
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.c_out0(c_out3),.c_out1(c_out4),.c_out2(c_out5),
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.c(c),.s(s));
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endmodule // oh_csa92
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