mirror of
https://github.com/aolofsson/oh.git
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19fa611bb9
- adding more chip code - pushing memory stuff into common - making common "oh_" naming class -
67 lines
2.8 KiB
Verilog
67 lines
2.8 KiB
Verilog
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// #
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// # This block converts encoded 5 bits
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// # into their decoded form of 32 bits
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// # In addition to the five bits encoded
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// # input, the block gets enable signal
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// # which results in all zeros on the
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// # output if disabled.
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// #
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module oh_decoder5 (/*AUTOARG*/
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// Outputs
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dec_out,
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// Inputs
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enc_in, enc_val
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);
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input [5:0] enc_in;
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input enc_val;
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output [31:0] dec_out;
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reg [31:0] dec_out;
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always @ (*)
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begin
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casez ({enc_val,enc_in[4:0]})
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6'b1_00000 : dec_out[31:0] = 32'b00000000000000000000000000000001;
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6'b1_00001 : dec_out[31:0] = 32'b00000000000000000000000000000010;
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6'b1_00010 : dec_out[31:0] = 32'b00000000000000000000000000000100;
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6'b1_00011 : dec_out[31:0] = 32'b00000000000000000000000000001000;
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6'b1_00100 : dec_out[31:0] = 32'b00000000000000000000000000010000;
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6'b1_00101 : dec_out[31:0] = 32'b00000000000000000000000000100000;
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6'b1_00110 : dec_out[31:0] = 32'b00000000000000000000000001000000;
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6'b1_00111 : dec_out[31:0] = 32'b00000000000000000000000010000000;
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6'b1_01000 : dec_out[31:0] = 32'b00000000000000000000000100000000;
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6'b1_01001 : dec_out[31:0] = 32'b00000000000000000000001000000000;
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6'b1_01010 : dec_out[31:0] = 32'b00000000000000000000010000000000;
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6'b1_01011 : dec_out[31:0] = 32'b00000000000000000000100000000000;
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6'b1_01100 : dec_out[31:0] = 32'b00000000000000000001000000000000;
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6'b1_01101 : dec_out[31:0] = 32'b00000000000000000010000000000000;
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6'b1_01110 : dec_out[31:0] = 32'b00000000000000000100000000000000;
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6'b1_01111 : dec_out[31:0] = 32'b00000000000000001000000000000000;
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6'b1_10000 : dec_out[31:0] = 32'b00000000000000010000000000000000;
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6'b1_10001 : dec_out[31:0] = 32'b00000000000000100000000000000000;
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6'b1_10010 : dec_out[31:0] = 32'b00000000000001000000000000000000;
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6'b1_10011 : dec_out[31:0] = 32'b00000000000010000000000000000000;
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6'b1_10100 : dec_out[31:0] = 32'b00000000000100000000000000000000;
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6'b1_10101 : dec_out[31:0] = 32'b00000000001000000000000000000000;
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6'b1_10110 : dec_out[31:0] = 32'b00000000010000000000000000000000;
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6'b1_10111 : dec_out[31:0] = 32'b00000000100000000000000000000000;
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6'b1_11000 : dec_out[31:0] = 32'b00000001000000000000000000000000;
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6'b1_11001 : dec_out[31:0] = 32'b00000010000000000000000000000000;
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6'b1_11010 : dec_out[31:0] = 32'b00000100000000000000000000000000;
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6'b1_11011 : dec_out[31:0] = 32'b00001000000000000000000000000000;
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6'b1_11100 : dec_out[31:0] = 32'b00010000000000000000000000000000;
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6'b1_11101 : dec_out[31:0] = 32'b00100000000000000000000000000000;
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6'b1_11110 : dec_out[31:0] = 32'b01000000000000000000000000000000;
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6'b1_11111 : dec_out[31:0] = 32'b10000000000000000000000000000000;
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default : dec_out[31:0] = 32'b00000000000000000000000000000000;
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endcase // casez ({enc_val,enc_in[4:0]})
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end // always @ (*)
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endmodule // oh_decoder5
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