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Andreas Olofsson 1e1644138e Splitting register file (rx,tx,base) 
The goal is to have 100% independence in RX and TX pipes
2015-04-23 17:50:45 -04:00
common
Adding emesh to packet converters
2015-04-22 16:43:52 -04:00
edma
Adding an emesh DMA
2015-04-23 17:49:06 -04:00
elink
Splitting register file (rx,tx,base)
2015-04-23 17:50:45 -04:00
embox
Adding basic readme files
2015-04-21 21:49:40 -04:00
emmu
MMU working...
2015-04-19 21:36:47 -04:00
memory
Adding basic readme files
2015-04-21 21:49:40 -04:00
xilibs
Cleanup
2015-04-22 13:56:29 -04:00
.gitignore
Cleanup
2015-04-21 21:43:16 -04:00
CONTRIBUTING.md
Basic infrastructure
2015-04-21 21:36:37 -04:00
COPYING
Basic infrastructure
2015-04-21 21:36:37 -04:00
LICENSE
Initial commit
2015-04-21 21:16:42 -04:00
README.md
Massive commit sequence coming...
2015-04-23 17:48:12 -04:00

README.md

=======

OH!

Open Hardware (Pure and Simple)

(work in progress...)

Description
No description provided
Readme MIT 43 MiB
Languages
Verilog 81.1%
Tcl 10.7%
C 5.6%
Shell 0.8%
Python 0.6%
Other 1.2%