Andreas Olofsson 1e1644138e Splitting register file (rx,tx,base) ...

The goal is to have 100% independence in RX and TX pipes

2015-04-23 17:50:45 -04:00

..

ecfg_if.v

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

ecfg_rx.v

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

ecfg_tx.v

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

ecfg.v

Message box working...

2015-04-19 21:55:07 -04:00

eclocks.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

elink_constants.v

Renaming constants file

2015-04-22 13:56:48 -04:00

elink_regmap.v

Message box working...

2015-04-19 21:55:07 -04:00

elink.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

emaxi.v

Bug fix, missing pipeline stage on read response

2015-04-21 17:14:30 -04:00

ememory.v

Implemented enesh memory

2015-04-21 17:13:09 -04:00

ereset.v

Cleanup

2015-04-18 16:26:32 -04:00

erx_disty.v

MILESTONE: Open souce simulation elink loopback working!

2015-04-17 15:51:55 -04:00

erx_io.v

Cleanup

2015-04-18 16:26:32 -04:00

erx_protocol.v

Verilator lint cleanup

2015-04-14 14:00:23 -04:00

erx.v

Cleanup

2015-04-18 16:26:32 -04:00

esaxi.v

Milestone: WRITE AND READ FROM HOST WORKS!

2015-04-21 17:16:20 -04:00

etx_arbiter.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

etx_io.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

etx_protocol.v

Clarified lclk names

2015-04-22 15:03:24 -04:00

etx.v

Clarified lclk names

2015-04-22 15:03:24 -04:00