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85 lines
2.1 KiB
Tcl
85 lines
2.1 KiB
Tcl
###########################################################
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#STEP0: Define variables
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set OUTDIR ./tmp
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set PART xc7z010clg400-1
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set TOP elink_example
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file mkdir $OUTDIR
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###########################################################
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#STEP1: Read sources, constraints, IP files
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create_project -in_memory -part $PART -force my_project
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source read_verilog.tcl
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source read_constraints.tcl
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source read_ip.tcl
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###########################################################
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#STEP2: SYNTHESIS
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###########################################################
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upgrade_ip [get_ips]
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generate_target all [get_ips]
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synth_ip [get_ips]
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synth_design -top $TOP -part $PART
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#create a checkpoint
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write_checkpoint -force $OUTDIR/post_syn.dcp
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#report timing
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report_timing_summary -file $OUTDIR/post_syn_timing_summary.rpt
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report_utilization -file $OUTDIR/post_syn_util.rpt
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###########################################################
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#STEP3: PLACEMENT
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###########################################################
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#optimize design
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opt_design
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#place design
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place_design
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#optimzier design
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phys_opt_design
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#create a checkpoint
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write_checkpoint -force $OUTDIR/post_place.dcp
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#post placement reporyts
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report_clock_utilization -file $OUTDIR/clock_util.rpt
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report_utilization -file $OUTDIR/post_place_util.rpt
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report_timing_summary -file $OUTDIR/post_place_timing_summary.rpt
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###########################################################
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#STEP4: ROUTING
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###########################################################
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#route design
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route_design
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#create checkpoint
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write_checkpoint -force $OUTDIR/post_route.dcp
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#create reports
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report_route_status -file $OUTDIR/post_route_status.rpt
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report_timing_summary -file $OUTDIR/post_route_timing_summary.rpt
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report_timing -sort_by group -max_paths 100 -path_type summary -file $OUTDIR/post_route_timing.rpt
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report_power -file $OUTDIR/post_route_power.rpt
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report_drc -file $OUTDIR/post_imp_drc.rpt
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###########################################################
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#STEP5: GENERATE BITSTREAM AND NETLIST
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###########################################################
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write_verilog -force $OUTDIR/$TOP.v
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write_xdc -no_fixed_only -force $OUTDIR/$TOP.xdc
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write_bitstream -force $OUTDIR/$TOP.bit
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