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315 lines
11 KiB
Verilog
315 lines
11 KiB
Verilog
module elink(/*AUTOARG*/
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// Outputs
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rx_lclk_div4, tx_lclk_div4, rxo_wr_wait_p, rxo_wr_wait_n,
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rxo_rd_wait_p, rxo_rd_wait_n, txo_lclk_p, txo_lclk_n, txo_frame_p,
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txo_frame_n, txo_data_p, txo_data_n, chipid, chip_resetb, cclk_p,
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cclk_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
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rxrr_access, rxrr_packet, txwr_wait, txrd_wait, txrr_wait,
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mailbox_not_empty, mailbox_full, timeout,
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// Inputs
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reset, pll_clkin, sys_clk, testmode, rxi_lclk_p, rxi_lclk_n,
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rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p,
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txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait,
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rxrr_wait, txwr_access, txwr_packet, txrd_access, txrd_packet,
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txrr_access, txrr_packet
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104; //packet width
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parameter ID = 12'h810;
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/****************************/
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/*CLK AND RESET */
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/****************************/
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input reset; // active high async reset
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input pll_clkin; // pll input clock
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input sys_clk; // system clock for FIFOs only
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input testmode; // places elink in testmode
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output rx_lclk_div4; // rx clock for synching with logic
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output tx_lclk_div4; // tx clock for synching with logic
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/********************************/
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/*ELINK I/O PINS */
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/********************************/
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//Receiver
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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input rxi_frame_p, rxi_frame_n; //link rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; //link rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
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//Transmitter
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output txo_lclk_p, txo_lclk_n; //link tx clock output
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output txo_frame_p, txo_frame_n; //link tx frame signal
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output [7:0] txo_data_p, txo_data_n; //link tx data
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input txi_wr_wait_p,txi_wr_wait_n; //link tx write pushback input
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input txi_rd_wait_p,txi_rd_wait_n; //link tx read pushback input
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/********************************/
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/*EPIPHANY INTERFACE (I/O PINS) */
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/********************************/
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output [11:0] chipid; // From etx of etx.v
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output chip_resetb; //chip reset for Epiphany (active low)
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output cclk_p, cclk_n; //high speed clock (up to 1GHz) to Epiphany
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/*****************************/
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/*"System" Interface */
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/*****************************/
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//Master Write (from RX)
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//Master Read Request (from RX)
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//Slave Read Response (from RX)
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//Slave Write (to TX)
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Slave Read Request (to TX)
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//Master Read Response (to TX)
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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/*****************************/
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/*MAILBOX (interrupts) */
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/*****************************/
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output mailbox_not_empty;
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output mailbox_full;
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/*****************************/
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/*READBACK TIMEOUT */
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/*****************************/
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output timeout;
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/*#############################################*/
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/* END OF BLOCK INTERFACE */
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/*#############################################*/
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/*AUTOINPUT*/
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// End of automatics
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//wires
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wire [31:0] mi_rd_data;
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wire [31:0] mi_dout_ecfg;
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wire [31:0] mi_dout_embox;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [15:0] clk_config; // From ecfg_clocks of ecfg_clocks.v
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wire elink_reset; // From ereset of ereset.v
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wire erx_cfg_access; // From ecfg_cdc of fifo_cdc.v
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wire [PW-1:0] erx_cfg_packet; // From ecfg_cdc of fifo_cdc.v
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wire erx_cfg_wait; // From erx of erx.v
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wire etx_cfg_access; // From etx of etx.v
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wire [PW-1:0] etx_cfg_packet; // From etx of etx.v
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wire etx_cfg_wait; // From ecfg_cdc of fifo_cdc.v
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wire soft_reset; // From ecfg_clocks of ecfg_clocks.v
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wire tx_lclk; // From eclocks of eclocks.v
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wire tx_lclk90; // From eclocks of eclocks.v
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// End of automatics
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/***********************************************************/
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/*CLOCK AND RESET CONFIG */
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/***********************************************************/
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defparam ecfg_clocks.ID=ID;
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ecfg_clocks ecfg_clocks (.hard_reset (reset),
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.clk (sys_clk),
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.txwr_access_out (txwr_gated_access),//filter access to etx
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/*AUTOINST*/
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// Outputs
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.soft_reset (soft_reset),
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.clk_config (clk_config[15:0]),
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// Inputs
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]));
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/***********************************************************/
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/*RESET CIRCUITRY */
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/***********************************************************/
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ereset ereset (.hard_reset (reset),
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/*AUTOINST*/
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// Outputs
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.elink_reset (elink_reset),
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.chip_resetb (chip_resetb),
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// Inputs
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.soft_reset (soft_reset));
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/***********************************************************/
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/*CLOCKS */
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/***********************************************************/
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eclocks eclocks (.hard_reset (reset),//reset by input pin only
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/*AUTOINST*/
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// Outputs
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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// Inputs
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.pll_clkin (pll_clkin));
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/***********************************************************/
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/*RECEIVER */
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/***********************************************************/
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/*erx AUTO_TEMPLATE (
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.mi_dout (mi_rx_dout[]),
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.emwr_\(.*\) (emaxi_emwr_\1[]),
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.emrq_\(.*\) (emaxi_emrq_\1[]),
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.emrr_\(.*\) (esaxi_emrr_\1[]),
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.reset (elink_reset),
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);
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*/
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defparam erx.ID=ID;
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erx erx(
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/*AUTOINST*/
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// Outputs
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.rx_lclk_div4 (rx_lclk_div4),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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.rxo_rd_wait_n (rxo_rd_wait_n),
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.erx_cfg_wait (erx_cfg_wait),
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.timeout (timeout),
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.mailbox_full (mailbox_full),
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.mailbox_not_empty (mailbox_not_empty),
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// Inputs
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.reset (elink_reset), // Templated
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.sys_clk (sys_clk),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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.rxi_frame_n (rxi_frame_n),
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.rxi_data_p (rxi_data_p[7:0]),
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.rxi_data_n (rxi_data_n[7:0]),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait),
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.erx_cfg_access (erx_cfg_access),
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.erx_cfg_packet (erx_cfg_packet[PW-1:0]));
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/***********************************************************/
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/*TRANSMITTER */
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/***********************************************************/
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/*etx AUTO_TEMPLATE (.mi_dout (mi_tx_dout[]),
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.emwr_\(.*\) (esaxi_emwr_\1[]),
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.emrq_\(.*\) (esaxi_emrq_\1[]),
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.emrr_\(.*\) (emaxi_emrr_\1[]),
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.reset (elink_reset),
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);
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*/
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defparam etx.ID=ID;
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etx etx(.txwr_access (txwr_gated_access),
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/*AUTOINST*/
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// Outputs
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.chipid (chipid[11:0]),
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.txo_lclk_p (txo_lclk_p),
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.txo_lclk_n (txo_lclk_n),
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.txo_frame_p (txo_frame_p),
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.txrd_wait (txrd_wait),
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.txwr_wait (txwr_wait),
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.txrr_wait (txrr_wait),
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.etx_cfg_access (etx_cfg_access),
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.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
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// Inputs
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.reset (elink_reset), // Templated
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.sys_clk (sys_clk),
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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.testmode (testmode),
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.txi_wr_wait_p (txi_wr_wait_p),
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.txi_wr_wait_n (txi_wr_wait_n),
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.txi_rd_wait_p (txi_rd_wait_p),
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.txi_rd_wait_n (txi_rd_wait_n),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]),
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.etx_cfg_wait (etx_cfg_wait));
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/***********************************************************/
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/*TX-->RX REGISTER INTERFACE CONNECTION */
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/***********************************************************/
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/*fifo_cdc AUTO_TEMPLATE (.clk_in (tx_lclk_div4),
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.clk_out (rx_lclk_div4),
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.packet_in (etx_cfg_packet[PW-1:0]),
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.packet_out (erx_cfg_packet[PW-1:0]),
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.access_in (etx_cfg_access),
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.access_out (erx_cfg_access),
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.reset (elink_reset),
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.wait_in (erx_cfg_wait),
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.wait_out (etx_cfg_wait),
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);
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*/
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defparam ecfg_cdc.WIDTH=104;
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defparam ecfg_cdc.DEPTH=16;
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fifo_cdc ecfg_cdc (/*AUTOINST*/
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// Outputs
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.wait_out (etx_cfg_wait), // Templated
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.access_out (erx_cfg_access), // Templated
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.packet_out (erx_cfg_packet[PW-1:0]), // Templated
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// Inputs
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.clk_in (tx_lclk_div4), // Templated
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.clk_out (rx_lclk_div4), // Templated
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.reset (elink_reset), // Templated
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.access_in (etx_cfg_access), // Templated
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.packet_in (etx_cfg_packet[PW-1:0]), // Templated
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.wait_in (erx_cfg_wait)); // Templated
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../erx/hdl" "../../etx/hdl" "../../memory/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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