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oh/stdlib/dv
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aolofsson de63dfd907 Major reorg! 
-stdcells moved to asiclib, doesn't make sense to be vectorized
-common is a stupid name, renamed as stdlib
2021-07-29 11:20:44 -04:00
..
tests
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cfg_random.v
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dut_clockdiv.v
Major reorg!
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dut_debouncer.v
Major reorg!
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dut_fifo_generic.v
Major reorg!
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dut_gray.v
Major reorg!
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dut_template.v
Major reorg!
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dv_driver.v
Major reorg!
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dv_random.v
Major reorg!
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dv_stimulus.v
Major reorg!
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dv_top.v
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firmware_example.hex
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libs.cmd
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oh_simchecker.v
Major reorg!
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oh_simctrl.v
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oh.gtkw
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README.md
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run.sh
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stimulus.v
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timescale.v
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README.md

What defines are used

iverilog -g2005 -DTARGET_SIM=1 $cfg $core.v $DV -f $LIBS -o $core.bin

How to compile all duts?

The script "build_all.sh" builds all dut files in this directory with random

./build_all.sh