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Andreas Olofsson 21173fef95 Forgot "posedge reset"
2015-04-23 20:05:51 -04:00
common
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
edma
Forgot "posedge reset"
2015-04-23 20:05:51 -04:00
elink
Fixed floating net bug
2015-04-23 20:05:00 -04:00
emailbox
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
emmu
Changing to packet interface
2015-04-23 17:54:23 -04:00
memory
Fixed stupid typos on full/empty
2015-04-23 18:56:49 -04:00
xilibs
Adding comments
2015-04-23 17:52:46 -04:00
.gitignore
Cleanup
2015-04-21 21:43:16 -04:00
CONTRIBUTING.md
Basic infrastructure
2015-04-21 21:36:37 -04:00
COPYING
Basic infrastructure
2015-04-21 21:36:37 -04:00
LICENSE
Initial commit
2015-04-21 21:16:42 -04:00
README.md
Massive commit sequence coming...
2015-04-23 17:48:12 -04:00

README.md

=======

OH!

Open Hardware (Pure and Simple)

(work in progress...)

Description
No description provided
Readme MIT 43 MiB
Languages
Verilog 81.1%
Tcl 10.7%
C 5.6%
Shell 0.8%
Python 0.6%
Other 1.2%