FPGA/oh

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Andreas Olofsson 21f87edd87 Memory bug fix

-srcaddr (upper data of read response) was using input instead of output data
-blocking upper data on 32 bit reads and smaller (quieter..)
Need random DV to flush out these silly bugs...

2015-04-26 08:29:50 -04:00

common

Verilator based lint cleanup

2015-04-23 18:57:55 -04:00

edma

Forgot "posedge reset"

2015-04-23 20:05:51 -04:00

elink

Memory bug fix

2015-04-26 08:29:50 -04:00

emailbox

Address remapping integration

2015-04-24 17:39:05 -04:00

emmu

Address remapping integration

2015-04-24 17:39:05 -04:00

memory

Made reset async (there may not be a clock..)

2015-04-24 17:32:17 -04:00

xilibs

Adding comments

2015-04-23 17:52:46 -04:00

.gitignore

Cleanup

2015-04-21 21:43:16 -04:00

CONTRIBUTING.md

Basic infrastructure

2015-04-21 21:36:37 -04:00

COPYING

Basic infrastructure

2015-04-21 21:36:37 -04:00

LICENSE

Initial commit

2015-04-21 21:16:42 -04:00

README.md

Massive commit sequence coming...

2015-04-23 17:48:12 -04:00

README.md

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OH!

Open Hardware (Pure and Simple)

(work in progress...)

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