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60 lines
1.4 KiB
Verilog
60 lines
1.4 KiB
Verilog
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/*###########################################################################
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# Function: Single port memory wrapper
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# To run without hardware platform dependancy use:
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# `define TARGET_CLEAN"
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############################################################################
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*/
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module oh_memory_sp(/*AUTOARG*/
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// Outputs
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dout,
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// Inputs
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clk, en, we, wem, addr, din
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);
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//parameters
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parameter DEPTH = 14;
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parameter DW = 32;
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parameter AW = $clog2(DEPTH);
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//interface
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input clk; //clock
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input en; //memory access
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input we; //write enable global signal
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input [DW-1:0] wem; //write enable vector
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input [AW-1:0] addr; //address
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input [DW-1:0] din; //data input
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output [DW-1:0] dout; //data output
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`ifdef CFG_ASIC
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initial
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$display("Need to instantiate process specific macro here");
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`else
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reg [DW-1:0] ram [DEPTH-1:0];
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reg [DW-1:0] dout;
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integer i;
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//read port (one cycle latency)
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always @ (posedge clk)
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if(en)
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dout[DW-1:0] <= ram[addr[AW-1:0]];
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//write port
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always @ (posedge clk)
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for(i=0;i<DW;i=i+1)
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if(en & wem[i] & we)
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ram[addr[AW-1:0]][i] <= din[i];
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`endif
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endmodule // oh_memory_sp
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