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495 lines
18 KiB
Verilog
495 lines
18 KiB
Verilog
module erx (/*AUTOARG*/
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// Outputs
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
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rxrr_packet, mi_dout, timeout,
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// Inputs
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reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
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rxi_data_p, rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait, mi_en,
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mi_we, mi_addr, mi_din, etx_read
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h800;
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//reset
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input reset;
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input sys_clk;
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//FROM IO Pins
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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input rxi_frame_p, rxi_frame_n; //link rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; //link rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
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//Master write
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//Master read request
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//Slave read response
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//Register Access Interface
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input mi_en;
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input mi_we;
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input [19:0] mi_addr;
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input [31:0] mi_din;
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output [31:0] mi_dout;
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//Starts timeout counter
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input etx_read;
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//Readback timeout
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output timeout;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire edma_access; // From edma of edma.v
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wire edma_wait; // From erx_disty of erx_disty.v
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wire emesh_remap_access; // From erx_remap of erx_remap.v
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wire [PW-1:0] emesh_remap_packet; // From erx_remap of erx_remap.v
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wire emmu_access; // From emmu of emmu.v
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wire [PW-1:0] emmu_packet; // From emmu of emmu.v
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wire erx_access; // From erx_protocol of erx_protocol.v
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wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v
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wire erx_rr; // From erx_protocol of erx_protocol.v
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wire erx_wait; // From erx_disty of erx_disty.v
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wire [8:0] gpio_datain; // From erx_io of erx_io.v
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wire [DW-1:0] mi_rx_cfg_dout; // From ecfg_rx of ecfg_rx.v
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wire [DW-1:0] mi_rx_edma_dout; // From edma of edma.v
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wire [DW-1:0] mi_rx_emmu_dout; // From emmu of emmu.v
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wire mmu_enable; // From ecfg_rx of ecfg_rx.v
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wire [31:0] remap_base; // From ecfg_rx of ecfg_rx.v
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wire [1:0] remap_mode; // From ecfg_rx of ecfg_rx.v
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wire [11:0] remap_pattern; // From ecfg_rx of ecfg_rx.v
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wire [11:0] remap_sel; // From ecfg_rx of ecfg_rx.v
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wire [63:0] rx_data_par; // From erx_io of erx_io.v
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wire rx_enable; // From ecfg_rx of ecfg_rx.v
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wire [7:0] rx_frame_par; // From erx_io of erx_io.v
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wire rx_lclk_div4; // From erx_io of erx_io.v
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wire rx_rd_wait; // From erx_disty of erx_disty.v
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wire rx_wr_wait; // From erx_disty of erx_disty.v
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wire rxrd_fifo_access; // From erx_disty of erx_disty.v
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wire [PW-1:0] rxrd_fifo_packet; // From erx_disty of erx_disty.v
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wire rxrd_fifo_wait; // From rxrd_fifo of fifo_async.v
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wire rxrr_fifo_access; // From erx_disty of erx_disty.v
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wire [PW-1:0] rxrr_fifo_packet; // From erx_disty of erx_disty.v
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wire rxrr_fifo_wait; // From rxrr_fifo of fifo_async.v
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wire rxwr_fifo_access; // From erx_disty of erx_disty.v
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wire [PW-1:0] rxwr_fifo_packet; // From erx_disty of erx_disty.v
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wire rxwr_fifo_wait; // From rxwr_fifo of fifo_async.v
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wire [1:0] timer_cfg; // From ecfg_rx of ecfg_rx.v
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// End of automatics
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//regs
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reg [15:0] debug_vector;
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wire rxwr_fifo_full;
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wire rxrr_fifo_full;
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wire rxrd_fifo_full;
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wire rxrd_empty;
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wire rxwr_empty;
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wire rxrr_empty;
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wire [103:0] edma_packet; // From edma of edma.v, ...
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/************************************************************/
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/* ERX CONFIGURATION */
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/************************************************************/
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defparam ecfg_rx.GROUP=`EGROUP_RX;
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/*ecfg_rx AUTO_TEMPLATE (.mi_dout (mi_rx_cfg_dout[DW-1:0]),
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);
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*/
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ecfg_rx ecfg_rx (.debug_vector (debug_vector[15:0]),
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_rx_cfg_dout[DW-1:0]), // Templated
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.rx_enable (rx_enable),
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.mmu_enable (mmu_enable),
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.remap_mode (remap_mode[1:0]),
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.remap_base (remap_base[31:0]),
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.remap_pattern (remap_pattern[11:0]),
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.remap_sel (remap_sel[11:0]),
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.timer_cfg (timer_cfg[1:0]),
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// Inputs
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.reset (reset),
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.sys_clk (sys_clk),
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.mi_en (mi_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[19:0]),
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.mi_din (mi_din[31:0]),
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.gpio_datain (gpio_datain[8:0]));
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/************************************************************/
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/* ERX READBACK MUX */
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/************************************************************/
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defparam ecfg_rx.GROUP=`EGROUP_RX;
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erx_mux erx_mux (/*AUTOINST*/
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// Outputs
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.mi_dout (mi_dout[DW-1:0]),
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// Inputs
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.sys_clk (sys_clk),
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.mi_en (mi_en),
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.mi_addr (mi_addr[19:0]),
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.mi_rx_cfg_dout (mi_rx_cfg_dout[DW-1:0]),
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.mi_rx_edma_dout (mi_rx_edma_dout[DW-1:0]),
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.mi_rx_emmu_dout (mi_rx_emmu_dout[DW-1:0]));
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/************************************************************/
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/* READ REQUEST TIMEOUT CIRCUIT */
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/************************************************************/
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/*erx_timer AUTO_TEMPLATE (.clk (rx_lclk_div4),
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.stop_count (rxrr_fifo_access),
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.start_count (etx_read),
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.erx_timeout (timeout),
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);
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*/
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erx_timer erx_timer(/*AUTOINST*/
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// Outputs
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.timeout (timeout),
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// Inputs
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.clk (rx_lclk_div4), // Templated
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.reset (reset),
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.timer_cfg (timer_cfg[1:0]),
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.stop_count (rxrr_fifo_access), // Templated
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.start_count (etx_read)); // Templated
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/************************************************************/
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/*FIFOs */
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/*(for AXI 1. read request, 2. write, and 3. read response) */
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/************************************************************/
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/*fifo_async AUTO_TEMPLATE (
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// Outputs
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.dout (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
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.empty (@"(substring vl-cell-name 0 4)"_empty),
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.full (@"(substring vl-cell-name 0 4)"_fifo_full),
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.prog_full (@"(substring vl-cell-name 0 4)"_fifo_wait),
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.valid (@"(substring vl-cell-name 0 4)"_access),
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// Inputs
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.rd_clk (sys_clk),
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.wr_clk (rx_lclk_div4),
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.wr_en (@"(substring vl-cell-name 0 4)"_fifo_access),
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.rd_en (~@"(substring vl-cell-name 0 4)"_wait & ~@"(substring vl-cell-name 0 4)"_empty),
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.reset (reset),
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.din (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
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);
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*/
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//Read request fifo (from Epiphany)
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fifo_async #(.DW(104), .AW(5))
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rxrd_fifo (.full (rxrd_fifo_full),
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.empty (rxrd_empty),
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/*AUTOINST*/
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// Outputs
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.prog_full (rxrd_fifo_wait), // Templated
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.dout (rxrd_packet[PW-1:0]), // Templated
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.valid (rxrd_access), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (rx_lclk_div4), // Templated
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.rd_clk (sys_clk), // Templated
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.wr_en (rxrd_fifo_access), // Templated
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.din (rxrd_fifo_packet[PW-1:0]), // Templated
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.rd_en (~rxrd_wait & ~rxrd_empty)); // Templated
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//Write fifo (from Epiphany)
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fifo_async #(.DW(104), .AW(5))
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rxwr_fifo(.full (rxwr_fifo_full),
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.empty (rxwr_empty),
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/*AUTOINST*/
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// Outputs
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.prog_full (rxwr_fifo_wait), // Templated
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.dout (rxwr_packet[PW-1:0]), // Templated
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.valid (rxwr_access), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (rx_lclk_div4), // Templated
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.rd_clk (sys_clk), // Templated
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.wr_en (rxwr_fifo_access), // Templated
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.din (rxwr_fifo_packet[PW-1:0]), // Templated
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.rd_en (~rxwr_wait & ~rxwr_empty)); // Templated
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//Read response fifo (for host)
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fifo_async #(.DW(104), .AW(5))
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rxrr_fifo(.full (rxrr_fifo_full),
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.empty (rxrr_empty),
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/*AUTOINST*/
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// Outputs
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.prog_full (rxrr_fifo_wait), // Templated
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.dout (rxrr_packet[PW-1:0]), // Templated
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.valid (rxrr_access), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (rx_lclk_div4), // Templated
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.rd_clk (sys_clk), // Templated
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.wr_en (rxrr_fifo_access), // Templated
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.din (rxrr_fifo_packet[PW-1:0]), // Templated
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.rd_en (~rxrr_wait & ~rxrr_empty)); // Templated
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/************************************************************/
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/*ELINK RECEIVE DISTRIBUTOR ("DEMUX") */
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/*(figures out who RX transaction belongs to) */
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/********************1***************************************/
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/*erx_disty AUTO_TEMPLATE (
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//Inputs
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.mmu_en (ecfg_rx_mmu_enable),
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.clk (rx_lclk_div4),
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)
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*/
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defparam erx_disty.ID = ID;
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erx_disty erx_disty (
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/*AUTOINST*/
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// Outputs
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.erx_wait (erx_wait),
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.rx_rd_wait (rx_rd_wait),
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.rx_wr_wait (rx_wr_wait),
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.edma_wait (edma_wait),
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.rxwr_fifo_access(rxwr_fifo_access),
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.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]),
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.rxrd_fifo_access(rxrd_fifo_access),
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.rxrd_fifo_packet(rxrd_fifo_packet[PW-1:0]),
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.rxrr_fifo_access(rxrr_fifo_access),
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.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
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// Inputs
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.erx_access (erx_access),
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.erx_packet (erx_packet[PW-1:0]),
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.emmu_access (emmu_access),
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.emmu_packet (emmu_packet[PW-1:0]),
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.edma_access (edma_access),
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.edma_packet (edma_packet[PW-1:0]),
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.rxwr_fifo_wait (rxwr_fifo_wait),
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.rxrd_fifo_wait (rxrd_fifo_wait),
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.rxrr_fifo_wait (rxrr_fifo_wait),
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.timeout (timeout));
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/************************************************************/
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/*ELINK DMA */
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/************************************************************/
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/*edma AUTO_TEMPLATE (.clk (rx_lclk_div4),
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.edma_access (edma_access),
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.mi_dout (mi_rx_edma_dout[DW-1:0]),
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.edma_access (edma_access),
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.edma_write (edma_packet[1]),
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.edma_datamode (edma_packet[3:2]),
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.edma_ctrlmode (edma_packet[7:4]),
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.edma_dstaddr (edma_packet[39:8]),
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.edma_data (edma_packet[71:40]),
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.edma_srcaddr (edma_packet[103:72]),
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);
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*/
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assign edma_packet[0]=edma_access;
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edma edma(/*AUTOINST*/
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// Outputs
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.mi_dout (mi_rx_edma_dout[DW-1:0]), // Templated
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.edma_access (edma_access), // Templated
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.edma_write (edma_packet[1]), // Templated
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.edma_datamode (edma_packet[3:2]), // Templated
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.edma_ctrlmode (edma_packet[7:4]), // Templated
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.edma_dstaddr (edma_packet[39:8]), // Templated
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.edma_data (edma_packet[71:40]), // Templated
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.edma_srcaddr (edma_packet[103:72]), // Templated
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// Inputs
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.reset (reset),
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.clk (rx_lclk_div4), // Templated
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.mi_en (mi_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[19:0]),
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.mi_din (mi_din[31:0]),
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.edma_wait (edma_wait));
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/************************************************************/
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/*ELINK MEMORY MANAGEMENT UNIT */
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/************************************************************/
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/*emmu AUTO_TEMPLATE (
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.emesh_\(.*\)_out (emmu_\1[]),
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//Inputs
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.emesh_\(.*\)_in (emesh_remap_\1[]),
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.mmu_en (mmu_enable),
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.emesh_clk (rx_lclk_div4),
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.mi_dout (mi_rx_emmu_dout[DW-1:0]),
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.emesh_packet_hi_out (),
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.mmu_bp (erx_rr),
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.emesh_wait_in (erx_wait),
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);
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*/
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defparam emmu.GROUP=`EGROUP_RX;
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emmu emmu (
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_rx_emmu_dout[DW-1:0]), // Templated
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.emesh_access_out (emmu_access), // Templated
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.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
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.emesh_packet_hi_out (), // Templated
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// Inputs
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.reset (reset),
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.sys_clk (sys_clk),
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.mmu_en (mmu_enable), // Templated
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.mmu_bp (erx_rr), // Templated
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.mi_en (mi_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[19:0]),
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.mi_din (mi_din[DW-1:0]),
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.emesh_clk (rx_lclk_div4), // Templated
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.emesh_access_in (emesh_remap_access), // Templated
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.emesh_packet_in (emesh_remap_packet[PW-1:0]), // Templated
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.emesh_wait_in (erx_wait)); // Templated
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/**************************************************************/
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/*ADDRESS REMPAPPING */
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/**************************************************************/
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//TODO: clean up signaling
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/*erx_remap AUTO_TEMPLATE (
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.emesh_\(.*\)_out (emesh_remap_\1[]),
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//Inputs
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.emesh_\(.*\)_in (erx_\1[]),
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.mmu_en (ecfg_rx_mmu_enable),
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.clk (rx_lclk_div4),
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.mi_dout (mi_rx_emmu_dout[DW-1:0]),
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.emesh_packet_hi_out (),
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.remap_bypass (erx_rr),
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);
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*/
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defparam erx_remap.ID = ID;
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erx_remap erx_remap (/*AUTOINST*/
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// Outputs
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.emesh_access_out(emesh_remap_access), // Templated
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.emesh_packet_out(emesh_remap_packet[PW-1:0]), // Templated
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// Inputs
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.clk (rx_lclk_div4), // Templated
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.reset (reset),
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.emesh_access_in(erx_access), // Templated
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.emesh_packet_in(erx_packet[PW-1:0]), // Templated
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.remap_mode (remap_mode[1:0]),
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.remap_sel (remap_sel[11:0]),
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.remap_pattern (remap_pattern[11:0]),
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.remap_base (remap_base[31:0]),
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.remap_bypass (erx_rr), // Templated
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.emesh_wait_in (erx_wait)); // Templated
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/**************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/**************************************************************/
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defparam erx_protocol.ID=ID;
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erx_protocol erx_protocol (/*AUTOINST*/
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// Outputs
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.erx_access (erx_access),
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.erx_packet (erx_packet[PW-1:0]),
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.erx_rr (erx_rr),
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// Inputs
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.reset (reset),
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.rx_enable (rx_enable),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_frame_par (rx_frame_par[7:0]),
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.rx_data_par (rx_data_par[63:0]));
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/***********************************************************/
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/*ELINK TRANSMIT I/O LOGIC */
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/***********************************************************/
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erx_io erx_io (
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/*AUTOINST*/
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// Outputs
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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|
.rxo_rd_wait_n (rxo_rd_wait_n),
|
|
.rx_lclk_div4 (rx_lclk_div4),
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|
.rx_frame_par (rx_frame_par[7:0]),
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|
.rx_data_par (rx_data_par[63:0]),
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.gpio_datain (gpio_datain[8:0]),
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|
// Inputs
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|
.reset (reset),
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|
.rxi_lclk_p (rxi_lclk_p),
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|
.rxi_lclk_n (rxi_lclk_n),
|
|
.rxi_frame_p (rxi_frame_p),
|
|
.rxi_frame_n (rxi_frame_n),
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|
.rxi_data_p (rxi_data_p[7:0]),
|
|
.rxi_data_n (rxi_data_n[7:0]),
|
|
.rx_wr_wait (rx_wr_wait),
|
|
.rx_rd_wait (rx_rd_wait));
|
|
|
|
/************************************************************/
|
|
/*Debug signals */
|
|
/************************************************************/
|
|
always @ (posedge sys_clk)
|
|
begin
|
|
debug_vector[15:0] <= {2'b0, //15:14
|
|
rx_rd_wait, //13
|
|
rx_wr_wait, //12
|
|
rxrr_wait, //11
|
|
rxrr_fifo_wait, //10
|
|
rxrr_fifo_access, //9
|
|
rxrd_wait, //8
|
|
rxrd_fifo_wait, //7
|
|
rxrd_fifo_access, //6
|
|
rxwr_wait, //5
|
|
rxwr_fifo_wait, //4
|
|
rxwr_fifo_access, //3
|
|
rxrr_fifo_full, //2
|
|
rxrd_fifo_full, //1
|
|
rxwr_fifo_full //0
|
|
};
|
|
end
|
|
|
|
|
|
endmodule // erx
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
|
|
// End:
|
|
|
|
/*
|
|
Copyright (C) 2014 Adapteva, Inc.
|
|
|
|
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
|
|
|
This program is free software: you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation, either version 3 of the License, or
|
|
(at your option) any later version.This program is distributed in the hope
|
|
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
|
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details. You should have received a copy
|
|
of the GNU General Public License along with this program (see the file
|
|
COPYING). If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|