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f544c44a08
-Access without symmetry was awkward, now we can reach regs from TX or RX side -Removes a special path for mailbox (came for free) -At the same time reduced clock complexity (one clock for system!!) -Moved mailbox to top level -Changed main clock to "sys_clk" for all
25 lines
470 B
Verilog
25 lines
470 B
Verilog
module erx_mux (/*AUTOARG*/
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// Outputs
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mi_dout,
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// Inputs
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sys_clk, mi_en, mi_addr, mi_rx_cfg_dout, mi_rx_edma_dout,
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mi_rx_emmu_dout
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);
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parameter DW = 32;
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parameter AW = 32;
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input sys_clk;
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//Needed for selecting data
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input mi_en;
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input [19:0] mi_addr;
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input [DW-1:0] mi_rx_cfg_dout;
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input [DW-1:0] mi_rx_edma_dout;
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input [DW-1:0] mi_rx_emmu_dout;
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output [DW-1:0] mi_dout;
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endmodule // erx_mux
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