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256 lines
8.2 KiB
Verilog
256 lines
8.2 KiB
Verilog
//########################################################################
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//# ELINK TX Protocol block
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//########################################################################
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//#
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//# The etx_protocol block implements a transmitter for communicating with
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//# the Epiphany receiver per the documentation seen below.
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//#
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//# The output transaction has an option of the bursting where data of
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//# the new transaction is sent without the address. In such a case the
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//# address of the transaction will be determined in the receiver according
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//# to the address of the previous transaction.
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//#
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//# ___ ___ ___ ___ ___ ___
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//# lclk _| |___| |___| |___| |___| |___| |_
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//#
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//# -------------------------------
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//# frame ______/
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//# --- --- --- --- ---
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//# data XXXXXXX 0 X 1 X 2 X 3 X 4 X .....
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//# --- --- --- --- ---
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//#
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//# Transaction structure:
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//# -------------------------
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//# byte0 -> 00000000
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//# byte1 -> ctrlmode[3:0],dstaddr[31:28]
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//# byte2 -> dstaddr[27:20]
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//# byte3 -> dstaddr[19:12]
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//# byte4 -> dstaddr[11:4]
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//# byte5 -> dstaddr[3:0],datamode[1:0],write,access
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//# byte6 -> data[31:24] (or srcaddr[31:24] if read transaction)
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//# byte7 -> data[23:16] (or srcaddr[23:16] if read transaction)
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//# byte8 -> data[15:8] (or srcaddr[15:8] if read transaction)
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//# *byte9 -> data[7:0] (or srcaddr[7:0] if read transaction)
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//# byte10 -> data[63:56]
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//# byte11 -> data[55:48]
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//# byte12 -> data[47:40]
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//# byte13 -> data[39:32]
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//# **byte14 -> data[31:24]
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//# ...
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//# ...
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//# ...
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//#
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//# * byte9 is the last byte of 32 bit write or read transaction
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//#
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//# ** if 64 bit write transaction, data of byte14 is the first data byte of
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//# bursting transaction
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//#
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//# -- The data is transmitted MSB first but in 32bits resolution. If we want
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//# to transmit 64 bits it will be [31:0] (msb first) and then [63:32]
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//# (msb first)
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//#
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//# Wait indication to the transmitter (from Epiphany chip receiver):
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//#
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//# When one of the secondary fifos becomes full we send wait indication
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//# to the transmitter.
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//# There is some uncertainty regarding how long it will take for the wait
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//# control to stop the transmitter (we have synchronization on the way,
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//# which may cause +/-1 cycle of uncertainty).
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//# Our main fifo on the input port of the receiver is robust enough
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//# (has enough entries) to receive all of the transactions sent during the
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//# time of "wait traveling" without loosing any information.
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//# But the uncertainty mentioned above forces us to start from empty fifo
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//# every time after wait indication is raised in order to ensure that
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//# the number of available entries won't be reduced.
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//#
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//#####################################################################
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module etx_protocol (/*AUTOARG*/
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// Outputs
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etx_rd_wait, etx_wr_wait, etx_wait, etx_io_wait, tx_frame_par,
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tx_data_par,
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// Inputs
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etx_access, etx_packet, ecfg_tx_tp_enable, ecfg_dataout,
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ecfg_tx_enable, ecfg_tx_gpio_enable, ecfg_access, ecfg_packet,
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reset, tx_lclk_div4, tx_rd_wait, tx_wr_wait
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);
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parameter PW = 104;
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parameter AW = 32;
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parameter DW = 32;
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//Bus side
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input etx_access;
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input [PW-1:0] etx_packet;
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output etx_rd_wait;
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output etx_wr_wait;
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output etx_wait; //for pipeline
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output etx_io_wait; //for arbiter
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//Enables transmit test pattern
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input ecfg_tx_tp_enable;
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input [8:0] ecfg_dataout;
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input ecfg_tx_enable;
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input ecfg_tx_gpio_enable;
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//Test Insertion
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input ecfg_access;
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input [PW-1:0] ecfg_packet;
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// IO side (8 eLink bytes at a time)
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input reset;
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input tx_lclk_div4;// Parallel-rate clock from eClock block
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output [7:0] tx_frame_par;
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output [63:0] tx_data_par;
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input tx_rd_wait; // The wait signals are passed through
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input tx_wr_wait; // to the emesh interfaces
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//############
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//# Local regs & wires
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//############
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reg etx_sample; //hold for second cycle
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reg [7:0] tx_frame_par;
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reg [127:0] tx_data_reg; //sample transaction on one clock cycle
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reg rd_wait_sync;
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reg wr_wait_sync;
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wire etx_write;
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wire [1:0] etx_datamode;
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wire [3:0] etx_ctrlmode;
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wire [AW-1:0] etx_dstaddr;
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wire [DW-1:0] etx_data;
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wire [AW-1:0] etx_srcaddr;
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wire access_mux;
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wire ecfg_access_sync;
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wire [PW-1:0] packet_mux;
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//Synchronize access signal
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synchronizer #(.DW(1)) synchronizer(.out (ecfg_access_sync),
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.in (ecfg_access),
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.clk (tx_lclk_div4),
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.reset (reset)
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);
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assign access_mux = ecfg_access_sync | etx_access;
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assign packet_mux[PW-1:0] = ecfg_access_sync ? ecfg_packet[PW-1:0] :
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etx_packet[PW-1:0];
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//packet to emesh bundle
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packet2emesh p2m (
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// Outputs
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.access_out (),
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.write_out (etx_write),
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.datamode_out (etx_datamode[1:0]),
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.ctrlmode_out (etx_ctrlmode[3:0]),
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.dstaddr_out (etx_dstaddr[31:0]),
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.data_out (etx_data[31:0]),
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.srcaddr_out (etx_srcaddr[31:0]),
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// Inputs
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.packet_in (packet_mux[PW-1:0]));
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// TODO: Bursts
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always @( posedge tx_lclk_div4 or posedge reset )
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begin
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if(reset)
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 8'd0;
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tx_data_reg[127:0] <= 'd0;
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end
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else
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begin
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if( access_mux & etx_sample ) //first cycle
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begin
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etx_sample <= 1'b0;
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tx_frame_par[7:0] <= 8'h3F;
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tx_data_reg[127:0] <= {etx_data[31:0],
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etx_srcaddr[31:0],
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8'd0, // Not used
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8'd0, //not used
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~etx_write, 7'd0, // B0-TODO: For bursts, add the inc bit
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etx_ctrlmode[3:0], etx_dstaddr[31:28], // B1
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etx_dstaddr[27:4], // B2, B3, B4
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etx_dstaddr[3:0], etx_datamode[1:0], etx_write, etx_access // B5
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};
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end
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else if(~etx_sample ) //second cycle (1)
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 8'hFF;
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end
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else
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begin
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etx_sample <= 1'b1;
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tx_frame_par[7:0] <= 'd0;
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tx_data_reg[127:0] <= 'd0;
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end
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end // else: !if(reset)
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end // always @ ( posedge txlclk_p or posedge reset )
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//After first sample, etx_sample-->0 use as indicator to sample in data.
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assign tx_data_par[63:0] = ~etx_sample ? tx_data_reg[63:0] : //first cycle
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tx_data_reg[127:64];//all others, 0 or upper
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//#############################
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//# Wait signals (async)
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//#############################
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synchronizer #(.DW(1)) rd_sync (// Outputs
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.out (etx_rd_wait),
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// Inputs
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.in (tx_rd_wait),
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.clk (tx_lclk_div4),
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.reset (reset)
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);
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synchronizer #(.DW(1)) wr_sync (// Outputs
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.out (etx_wr_wait),
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// Inputs
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.in (tx_wr_wait),
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.clk (tx_lclk_div4),
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.reset (reset)
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);
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//#############################
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//# Pipeline stall
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//#############################
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assign etx_io_wait = ~etx_sample;
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assign etx_wait = etx_io_wait |
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etx_rd_wait |
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etx_wr_wait;
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endmodule // etx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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File: etx_protocol.v
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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