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https://github.com/aolofsson/oh.git
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382 lines
13 KiB
Verilog
382 lines
13 KiB
Verilog
//`timescale 1 ns / 100 ps
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module dv_elink();
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parameter DW = 32;
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parameter AW = 32;
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//Basic stimulus to drive
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reg hw_reset; //active high asynchronous hardware reset
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reg clkin; //primary clock reg
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reg rx_lclk_p; //linkh speed clock reg (up to 500MHz)
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wire rx_lclk_n;
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reg rx_frame_p; //transaction frame signal
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wire rx_frame_n;
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reg [7:0] rx_data_p; //receive data (dual data rate)
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wire [7:0] rx_data_n;
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reg tx_wr_wait_p; //incoming pushback on write transactions
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wire tx_wr_wait_n;
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reg tx_rd_wait_p; //incoming pushback on read transactions
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wire tx_rd_wait_n;
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reg m_axi_aclk;
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reg m_axi_aresetn;
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reg m_axi_arready; //read ready
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reg m_axi_awready;
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reg [0:0] m_axi_bid; //response tag
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reg [1:0] m_axi_bresp;
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reg m_axi_bvalid;
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reg [63:0] m_axi_rdata;
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reg [0:0] m_axi_rid; //read id tag
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reg m_axi_rlast; //indicates last transfer of a burst
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reg [1:0] m_axi_rresp;
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reg m_axi_rvalid;
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reg m_axi_wready; //response ready
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reg s_axi_aclk;
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reg s_axi_aresetn;
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reg [29:0] s_axi_araddr;
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reg [1:0] s_axi_arburst;
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reg [3:0] s_axi_arcache;
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reg [11:0] s_axi_arid;
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reg [7:0] s_axi_arlen;
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reg [0:0] s_axi_arlock;
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reg [2:0] s_axi_arprot;
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reg [3:0] s_axi_arqos;
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reg [3:0] s_axi_arregion;
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reg [2:0] s_axi_arsize;
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reg s_axi_arvalid;
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reg [29:0] s_axi_awaddr;
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reg [1:0] s_axi_awburst;
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reg [3:0] s_axi_awcache;
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reg [11:0] s_axi_awid;
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reg [7:0] s_axi_awlen;
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reg [0:0] s_axi_awlock;
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reg [2:0] s_axi_awprot;
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reg [3:0] s_axi_awqos;
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reg [3:0] s_axi_awregion;
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reg [2:0] s_axi_awsize;
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reg s_axi_awvalid;
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reg s_axi_bready;
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reg s_axi_rready;
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reg [31:0] s_axi_wdata;
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reg s_axi_wlast;
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reg [3:0] s_axi_wstrb;
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reg s_axi_wvalid;
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reg s_axicfg_aclk;
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reg s_axicfg_aresetn;
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reg [12:0] s_axicfg_araddr;
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reg [2:0] s_axicfg_arprot;
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reg s_axicfg_arvalid;
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reg [12:0] s_axicfg_awaddr;
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reg [2:0] s_axicfg_awprot;
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reg s_axicfg_bready;
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reg s_axicfg_rready;
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reg [31:0] s_axicfg_wdata;
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reg [3:0] s_axicfg_wstrb;
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reg s_axicfg_wvalid;
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//Reset
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initial
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begin
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$display($time, " << Starting the Simulation >>");
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#0
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hw_reset = 1'b1;
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clkin = 1'b0;
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rx_lclk_p = 1'b0;
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rx_frame_p = 1'b0;
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rx_data_p[7:0] = 8'h00;
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tx_wr_wait_p = 1'b0;
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tx_rd_wait_p = 1'b0;
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m_axi_aclk = 1'b0;
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m_axi_aresetn = 1'b0;
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m_axi_arready = 1'b0;
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m_axi_awready = 1'b0;
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m_axi_bid = 1'b0;
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m_axi_bresp[1:0] = 2'b0;
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m_axi_bvalid = 1'b0;
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m_axi_rdata[63:0] = 64'b0;
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m_axi_rid[0:0] = 1'b0;
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m_axi_rlast = 1'b0;
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m_axi_rresp[1:0] = 2'b0;
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m_axi_rvalid = 1'b0;
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m_axi_wready = 1'b0;
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s_axi_aclk = 1'b0;
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s_axi_aresetn = 1'b0;
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s_axi_araddr[29:0]= 30'b0;
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s_axi_arburst[1:0]= 2'b0;
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s_axi_arcache[3:0]= 4'b0;
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s_axi_arid[11:0] = 12'b0;
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s_axi_arlen[7:0] = 8'b0;
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s_axi_arlock[0:0] = 1'b0;
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s_axi_arprot[2:0] = 2'b0;
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s_axi_arqos[3:0] = 4'b0;
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s_axi_arregion[3:0]=4'b0;
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s_axi_arsize[2:0] = 2'b0;
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s_axi_arvalid = 1'b0;
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s_axi_awaddr[29:0]= 30'b0;
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s_axi_awburst[1:0]= 2'b0;
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s_axi_awcache[3:0]= 4'b0;
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s_axi_awid[11:0] = 12'b0;
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s_axi_awlen[7:0] = 8'b0;
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s_axi_awlock[0:0] = 1'b0;
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s_axi_awprot[2:0] = 3'b0;
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s_axi_awqos[3:0] = 4'b0;
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s_axi_awregion[3:0]= 4'b0;
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s_axi_awsize[2:0] = 3'b0;
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s_axi_awvalid = 1'b0;
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s_axi_bready = 1'b0;
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s_axi_rready = 1'b0;
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s_axi_wdata[31:0] = 32'b0;
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s_axi_wlast = 1'b0;
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s_axi_wstrb[3:0] = 4'b0;
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s_axi_wvalid = 1'b0;
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s_axicfg_aclk = 1'b0;
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s_axicfg_aresetn = 1'b0;
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s_axicfg_araddr[12:0]=13'b0;
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s_axicfg_arprot[2:0] = 1'b0;
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s_axicfg_arvalid = 1'b0;
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s_axicfg_awaddr[12:0]= 13'b0;
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s_axicfg_awprot[2:0] = 3'b0;
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s_axicfg_bready = 1'b0;
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s_axicfg_rready = 1'b0;
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s_axicfg_wdata[31:0] = 32'b0;
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s_axicfg_wstrb[3:0] = 4'b0;
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s_axicfg_wvalid = 1'b0;
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#100
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hw_reset = 1'b0; // at time 100 release reset
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#10000
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$finish;
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end
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//Clock
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always
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begin
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#10
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begin
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clkin = ~clkin;
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rx_lclk_p = ~rx_lclk_p;
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s_axi_aclk = ~s_axi_aclk;
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m_axi_aclk = ~m_axi_aclk;
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s_axicfg_aclk=~s_axicfg_aclk;
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end
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end
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//Driving differentials
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assign rx_clk_n = ~rx_lclk_p;
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assign rx_frame_n = ~rx_frame_p;
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assign rx_data_n = ~rx_data_p;
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assign tx_wr_wait_n = ~tx_wr_wait_p;
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assign tx_rd_wait_n = ~tx_rd_wait_p;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire cclk_n; // From elink of elink.v
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wire cclk_p; // From elink of elink.v
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wire [3:0] colid; // From elink of elink.v
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wire embox_full; // From elink of elink.v
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wire embox_not_empty; // From elink of elink.v
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wire [31:0] m_axi_araddr; // From elink of elink.v
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wire [1:0] m_axi_arburst; // From elink of elink.v
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wire [3:0] m_axi_arcache; // From elink of elink.v
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wire [0:0] m_axi_arid; // From elink of elink.v
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wire [7:0] m_axi_arlen; // From elink of elink.v
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wire [0:0] m_axi_arlock; // From elink of elink.v
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wire [2:0] m_axi_arprot; // From elink of elink.v
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wire [3:0] m_axi_arqos; // From elink of elink.v
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wire [2:0] m_axi_arsize; // From elink of elink.v
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wire m_axi_arvalid; // From elink of elink.v
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wire [31:0] m_axi_awaddr; // From elink of elink.v
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wire [1:0] m_axi_awburst; // From elink of elink.v
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wire [3:0] m_axi_awcache; // From elink of elink.v
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wire [0:0] m_axi_awid; // From elink of elink.v
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wire [7:0] m_axi_awlen; // From elink of elink.v
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wire [0:0] m_axi_awlock; // From elink of elink.v
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wire [2:0] m_axi_awprot; // From elink of elink.v
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wire [3:0] m_axi_awqos; // From elink of elink.v
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wire [2:0] m_axi_awsize; // From elink of elink.v
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wire m_axi_awvalid; // From elink of elink.v
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wire m_axi_bready; // From elink of elink.v
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wire m_axi_rready; // From elink of elink.v
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wire [63:0] m_axi_wdata; // From elink of elink.v
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wire m_axi_wlast; // From elink of elink.v
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wire [7:0] m_axi_wstrb; // From elink of elink.v
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wire m_axi_wvalid; // From elink of elink.v
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wire reset_n; // From elink of elink.v
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wire [3:0] rowid; // From elink of elink.v
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wire rx_rd_wait_n; // From elink of elink.v
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wire rx_rd_wait_p; // From elink of elink.v
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wire rx_wr_wait_n; // From elink of elink.v
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wire rx_wr_wait_p; // From elink of elink.v
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wire s_axi_arready; // From elink of elink.v
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wire s_axi_awready; // From elink of elink.v
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wire [11:0] s_axi_bid; // From elink of elink.v
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wire [1:0] s_axi_bresp; // From elink of elink.v
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wire s_axi_bvalid; // From elink of elink.v
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wire [31:0] s_axi_rdata; // From elink of elink.v
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wire [11:0] s_axi_rid; // From elink of elink.v
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wire s_axi_rlast; // From elink of elink.v
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wire [1:0] s_axi_rresp; // From elink of elink.v
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wire s_axi_rvalid; // From elink of elink.v
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wire s_axi_wready; // From elink of elink.v
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wire s_axicfg_arready; // From elink of elink.v
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wire s_axicfg_awready; // From elink of elink.v
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wire [1:0] s_axicfg_bresp; // From elink of elink.v
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wire s_axicfg_bvalid; // From elink of elink.v
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wire [31:0] s_axicfg_rdata; // From elink of elink.v
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wire [1:0] s_axicfg_rresp; // From elink of elink.v
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wire s_axicfg_rvalid; // From elink of elink.v
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wire s_axicfg_wready; // From elink of elink.v
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wire [7:0] tx_data_n; // From elink of elink.v
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wire [7:0] tx_data_p; // From elink of elink.v
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wire tx_frame_n; // From elink of elink.v
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wire tx_frame_p; // From elink of elink.v
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wire tx_lclk_n; // From elink of elink.v
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wire tx_lclk_p; // From elink of elink.v
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// End of automatics
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elink elink (/*AUTOINST*/
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// Outputs
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.rowid (rowid[3:0]),
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.colid (colid[3:0]),
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.reset_n (reset_n),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.rx_wr_wait_p (rx_wr_wait_p),
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.rx_wr_wait_n (rx_wr_wait_n),
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.rx_rd_wait_p (rx_rd_wait_p),
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.rx_rd_wait_n (rx_rd_wait_n),
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.tx_lclk_p (tx_lclk_p),
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.tx_lclk_n (tx_lclk_n),
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.tx_frame_p (tx_frame_p),
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.tx_frame_n (tx_frame_n),
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.tx_data_p (tx_data_p[7:0]),
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.tx_data_n (tx_data_n[7:0]),
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.embox_not_empty (embox_not_empty),
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.embox_full (embox_full),
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.m_axi_araddr (m_axi_araddr[31:0]),
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.m_axi_arburst (m_axi_arburst[1:0]),
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.m_axi_arcache (m_axi_arcache[3:0]),
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.m_axi_arid (m_axi_arid[0:0]),
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.m_axi_arlen (m_axi_arlen[7:0]),
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.m_axi_arlock (m_axi_arlock[0:0]),
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.m_axi_arprot (m_axi_arprot[2:0]),
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.m_axi_arqos (m_axi_arqos[3:0]),
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.m_axi_arsize (m_axi_arsize[2:0]),
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.m_axi_arvalid (m_axi_arvalid),
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.m_axi_awaddr (m_axi_awaddr[31:0]),
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.m_axi_awburst (m_axi_awburst[1:0]),
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.m_axi_awcache (m_axi_awcache[3:0]),
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.m_axi_awid (m_axi_awid[0:0]),
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.m_axi_awlen (m_axi_awlen[7:0]),
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.m_axi_awlock (m_axi_awlock[0:0]),
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.m_axi_awprot (m_axi_awprot[2:0]),
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.m_axi_awqos (m_axi_awqos[3:0]),
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.m_axi_awsize (m_axi_awsize[2:0]),
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.m_axi_awvalid (m_axi_awvalid),
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.m_axi_bready (m_axi_bready),
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.m_axi_rready (m_axi_rready),
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.m_axi_wdata (m_axi_wdata[63:0]),
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.m_axi_wlast (m_axi_wlast),
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.m_axi_wstrb (m_axi_wstrb[7:0]),
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.m_axi_wvalid (m_axi_wvalid),
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.s_axi_arready (s_axi_arready),
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.s_axi_awready (s_axi_awready),
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.s_axi_bid (s_axi_bid[11:0]),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_rdata (s_axi_rdata[31:0]),
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.s_axi_rid (s_axi_rid[11:0]),
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.s_axi_rlast (s_axi_rlast),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_wready (s_axi_wready),
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.s_axicfg_arready (s_axicfg_arready),
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.s_axicfg_awready (s_axicfg_awready),
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.s_axicfg_bresp (s_axicfg_bresp[1:0]),
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.s_axicfg_bvalid (s_axicfg_bvalid),
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.s_axicfg_rdata (s_axicfg_rdata[31:0]),
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.s_axicfg_rresp (s_axicfg_rresp[1:0]),
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.s_axicfg_rvalid (s_axicfg_rvalid),
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.s_axicfg_wready (s_axicfg_wready),
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// Inputs
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.hw_reset (hw_reset),
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.clkin (clkin),
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.rx_lclk_p (rx_lclk_p),
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.rx_lclk_n (rx_lclk_n),
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.rx_frame_p (rx_frame_p),
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.rx_frame_n (rx_frame_n),
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.rx_data_p (rx_data_p[7:0]),
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.rx_data_n (rx_data_n[7:0]),
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.tx_wr_wait_p (tx_wr_wait_p),
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.tx_wr_wait_n (tx_wr_wait_n),
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.tx_rd_wait_p (tx_rd_wait_p),
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.tx_rd_wait_n (tx_rd_wait_n),
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.m_axi_aclk (m_axi_aclk),
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.m_axi_aresetn (m_axi_aresetn),
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.m_axi_arready (m_axi_arready),
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.m_axi_awready (m_axi_awready),
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.m_axi_bid (m_axi_bid[0:0]),
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.m_axi_bresp (m_axi_bresp[1:0]),
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.m_axi_bvalid (m_axi_bvalid),
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.m_axi_rdata (m_axi_rdata[63:0]),
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.m_axi_rid (m_axi_rid[0:0]),
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.m_axi_rlast (m_axi_rlast),
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.m_axi_rresp (m_axi_rresp[1:0]),
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.m_axi_rvalid (m_axi_rvalid),
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.m_axi_wready (m_axi_wready),
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_araddr (s_axi_araddr[29:0]),
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.s_axi_arburst (s_axi_arburst[1:0]),
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.s_axi_arcache (s_axi_arcache[3:0]),
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.s_axi_arid (s_axi_arid[11:0]),
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.s_axi_arlen (s_axi_arlen[7:0]),
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.s_axi_arlock (s_axi_arlock[0:0]),
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.s_axi_arprot (s_axi_arprot[2:0]),
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.s_axi_arqos (s_axi_arqos[3:0]),
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.s_axi_arregion (s_axi_arregion[3:0]),
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.s_axi_arsize (s_axi_arsize[2:0]),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_awaddr (s_axi_awaddr[29:0]),
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.s_axi_awburst (s_axi_awburst[1:0]),
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.s_axi_awcache (s_axi_awcache[3:0]),
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.s_axi_awid (s_axi_awid[11:0]),
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.s_axi_awlen (s_axi_awlen[7:0]),
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.s_axi_awlock (s_axi_awlock[0:0]),
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.s_axi_awprot (s_axi_awprot[2:0]),
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.s_axi_awqos (s_axi_awqos[3:0]),
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.s_axi_awregion (s_axi_awregion[3:0]),
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.s_axi_awsize (s_axi_awsize[2:0]),
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|
.s_axi_awvalid (s_axi_awvalid),
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.s_axi_bready (s_axi_bready),
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|
.s_axi_rready (s_axi_rready),
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|
.s_axi_wdata (s_axi_wdata[31:0]),
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|
.s_axi_wlast (s_axi_wlast),
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|
.s_axi_wstrb (s_axi_wstrb[3:0]),
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|
.s_axi_wvalid (s_axi_wvalid),
|
|
.s_axicfg_aclk (s_axicfg_aclk),
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|
.s_axicfg_aresetn (s_axicfg_aresetn),
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|
.s_axicfg_araddr (s_axicfg_araddr[12:0]),
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|
.s_axicfg_arprot (s_axicfg_arprot[2:0]),
|
|
.s_axicfg_arvalid (s_axicfg_arvalid),
|
|
.s_axicfg_awaddr (s_axicfg_awaddr[12:0]),
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|
.s_axicfg_awprot (s_axicfg_awprot[2:0]),
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|
.s_axicfg_awvalid (s_axicfg_awvalid),
|
|
.s_axicfg_bready (s_axicfg_bready),
|
|
.s_axicfg_rready (s_axicfg_rready),
|
|
.s_axicfg_wdata (s_axicfg_wdata[31:0]),
|
|
.s_axicfg_wstrb (s_axicfg_wstrb[3:0]),
|
|
.s_axicfg_wvalid (s_axicfg_wvalid));
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|
|
|
//Waveform dump
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|
initial
|
|
begin
|
|
$dumpfile("test.vcd");
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|
$dumpvars(0, dv_elink);
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|
end
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|
|
|
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|
endmodule // dv_elink
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|
// Local Variables:
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|
// verilog-library-directories:("." "../hdl")
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|
// End:
|