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b0b9315bf1
-this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created)
19 lines
646 B
Markdown
19 lines
646 B
Markdown
##DIRECTORY STRUCTURE
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* **elink**: Top level elink block
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* **axi**: Master and slave interface for elink
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* **common**: Various reusable blocks
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* **eclock**: Drives all clocks for elink and epiphany
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* **ecfg**: Configuration register file for the elink
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* **gpio**: GPIO block
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* **i2c**: I2C wrapper
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* **etx**: The elink transmitter logic
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* **erx**: The elink receiver logic
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* **memory**: Memory wrappers
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* **emmu**: Memory management unit
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* **embox**: Mailbox with interrupts
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##DIRECTORY CONTENT
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Each block should be considered a reusabel entitity and include
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hdl source code as well as a basic test environment.
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