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66 lines
3.2 KiB
Verilog
66 lines
3.2 KiB
Verilog
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
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// Date : Wed Apr 8 17:09:37 2015
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// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
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// Command : write_verilog -force -mode synth_stub
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// /home/aolofsson/Work_all/parallella-hw/fpga/vivado/archives/parallella_7020_headless_gpiose_elink2/parallella_7020_headless_gpiose_elink2.srcs/sources_1/ip/axi_bram_ctrl_16b/axi_bram_ctrl_16b_stub.v
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// Design : axi_bram_ctrl_16b
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg400-1
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "axi_bram_ctrl,Vivado 2014.3.1" *)
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module axi_bram_ctrl_16b(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a)
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/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0]" */;
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input s_axi_aclk;
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input s_axi_aresetn;
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input [15:0]s_axi_awaddr;
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input [2:0]s_axi_awprot;
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input s_axi_awvalid;
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output s_axi_awready;
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input [31:0]s_axi_wdata;
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input [3:0]s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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output [1:0]s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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input [15:0]s_axi_araddr;
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input [2:0]s_axi_arprot;
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input s_axi_arvalid;
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output s_axi_arready;
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output [31:0]s_axi_rdata;
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output [1:0]s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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output bram_rst_a;
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output bram_clk_a;
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output bram_en_a;
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output [3:0]bram_we_a;
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output [15:0]bram_addr_a;
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output [31:0]bram_wrdata_a;
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input [31:0]bram_rddata_a;
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//dummy outputs
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assign s_axi_awready=1'b0;
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assign s_axi_wready=1'b0;
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assign s_axi_bresp[1:0]=2'b0;
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assign s_axi_bvalid=1'b0;
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assign s_axi_arready=1'b0;
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assign s_axi_rdata[31:0]=32'b0;
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assign s_axi_rresp[1:0]=2'b0;
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assign s_axi_rvalid=1'b0;
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assign bram_rst_a=1'b0;
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assign bram_clk_a=s_axi_aclk;
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assign bram_en_a=1'b0;
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assign bram_we_a [3:0]=4'b0;
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assign bram_addr_a[15:0]=16'b0;
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assign bram_wrdata_a[31:0]=32'b0;
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endmodule
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