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de63dfd907
-stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib
79 lines
2.8 KiB
Verilog
79 lines
2.8 KiB
Verilog
//#############################################################################
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//# Function: Dual Ported Memory #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_memory_dp
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#(parameter N = 32, // FIFO width
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parameter DEPTH = 32, // FIFO depth
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parameter REG = 1, // Register fifo output
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parameter SYN = "TRUE", // hard (macro) or soft (rtl)
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parameter TYPE = "DEFAULT", // pass through variable for hard macro
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parameter SHAPE = "SQUARE", // hard macro shape (square, tall, wide)
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parameter AW = $clog2(DEPTH) // rd_count width (derived)
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)
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(// Memory interface (dual port)
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input wr_clk, //write clock
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input wr_en, //write enable
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input [N-1:0] wr_wem, //per bit write enable
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input [AW-1:0] wr_addr,//write address
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input [N-1:0] wr_din, //write data
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input rd_clk, //read clock
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input rd_en, //read enable
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input [AW-1:0] rd_addr,//read address
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output [N-1:0] rd_dout,//read output data
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// BIST interface
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input bist_en, // bist enable
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input bist_we, // write enable global signal
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input [N-1:0] bist_wem, // write enable vector
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input [AW-1:0] bist_addr, // address
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input [N-1:0] bist_din, // data input
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// Power/repair (hard macro only)
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input shutdown, // shutdown signal
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input vss, // ground signal
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input vdd, // memory array power
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input vddio, // periphery/io power
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input [7:0] memconfig, // generic memory config
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input [7:0] memrepair // repair vector
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);
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generate
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if(SYN == "TRUE") begin
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//#########################################
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// Generic RAM for synthesis
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//#########################################
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//local variables
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reg [N-1:0] ram [0:DEPTH-1];
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wire [N-1:0] rdata;
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integer i;
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//write port
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always @(posedge wr_clk)
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for (i=0;i<N;i=i+1)
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if (wr_en & wr_wem[i])
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ram[wr_addr[AW-1:0]][i] = wr_din[i];
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//read port
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assign rdata[N-1:0] = ram[rd_addr[AW-1:0]];
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//Configurable output register
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reg [N-1:0] rd_reg;
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always @ (posedge rd_clk)
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if(rd_en)
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rd_reg[N-1:0] <= rdata[N-1:0];
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//Drive output from register or RAM directly
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assign rd_dout[N-1:0] = (REG==1) ? rd_reg[N-1:0] : rdata[N-1:0];
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end // block: soft
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else begin
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asic_memory_dp #(.N(N),
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.DEPTH(DEPTH),
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.SHAPE(SHAPE),
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.REG(REG))
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asic_memory_dp ();
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end // block: hard
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endgenerate
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endmodule // oh_memory_dp
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