mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-17 20:02:53 +08:00
374 lines
9.9 KiB
Verilog
374 lines
9.9 KiB
Verilog
/*
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This block receives the IO transaction and converts to a 104 bit packet.
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*/
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module erx_io (/*AUTOARG*/
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// Outputs
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rx_clkin, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
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// Inputs
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erx_io_nreset, rx_lclk, rx_lclk_div4, idelay_value, load_taps,
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rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
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rxi_data_n, rx_wr_wait, rx_rd_wait
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);
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parameter IOSTD_ELINK = "LVDS_25";
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parameter PW = 104;
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parameter ETYPE = 1;//0=parallella
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//1=ephycard
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//#########################
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//# reset, clocks
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//#########################
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input erx_io_nreset; // high sped reset
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input rx_lclk; // fast I/O clock
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input rx_lclk_div4; // slow clock
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output rx_clkin; // clock output for pll
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//#########################
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//# idelays
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//#########################
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input [44:0] idelay_value;
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input load_taps;
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//##########################
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//# elink pins
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//##########################
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input rxi_lclk_p, rxi_lclk_n; // rx clock input
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input rxi_frame_p, rxi_frame_n; // rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; // rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
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//##########################
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//# erx logic interface
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//##########################
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output rx_access;
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output rx_burst;
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output [PW-1:0] rx_packet;
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input rx_wr_wait;
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input rx_rd_wait;
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//############
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//# WIRES
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//############
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wire [7:0] rxi_data;
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wire rxi_frame;
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wire rxi_lclk;
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wire access_wide;
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wire [15:0] rx_word_iddr;
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wire rx_frame_iddr;
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//############
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//# REGS
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//############
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reg valid_packet;
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reg [15:0] rx_word_sync;
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reg [111:0] rx_sample;
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reg [6:0] rx_pointer;
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reg access;
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reg burst;
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reg [PW-1:0] rx_packet_lclk;
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reg rx_access;
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reg [PW-1:0] rx_packet;
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reg rx_burst;
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wire [8:0] rxi_delay_in;
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wire [8:0] rxi_delay_out;
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reg burst_detect;
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reg [3:0] valid;
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//#########################################
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//# Pins inverted for 64-core board
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//#########################################
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`ifdef TARGET_E64
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assign invert_pins=1'b1;
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`else
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assign invert_pins=1'b0;
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`endif
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//#######################################
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//#Register DDR inputs for better timing
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//#######################################
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reg rx_frame;
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reg [15:0] rx_word;
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always @ (posedge rx_lclk)
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begin
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rx_frame <= rx_frame_iddr;
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rx_word[15:0] <= rx_word_iddr[15:0];
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end
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//#####################
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//#CREATE 112 BIT PACKET
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//#####################
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//write Pointer
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always @ (posedge rx_lclk or negedge erx_io_nreset)
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if(!erx_io_nreset)
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rx_pointer[6:0] <= 7'b0;
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else if (~rx_frame)
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rx_pointer[6:0] <= 7'b0000001; //new frame
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else if (rx_pointer[6])
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rx_pointer[6:0] <= 7'b0001000; //anticipate burst
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else if(rx_frame)
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rx_pointer[6:0] <= {rx_pointer[5:0],1'b0};//middle of frame
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//convert to 112 bit packet
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always @ (posedge rx_lclk)
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begin
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if(rx_pointer[0])
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rx_sample[15:0] <= rx_word[15:0];
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if(rx_pointer[1])
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rx_sample[31:16] <= rx_word[15:0];
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if(rx_pointer[2])
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rx_sample[47:32] <= rx_word[15:0];
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if(rx_pointer[3])
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rx_sample[63:48] <= rx_word[15:0];
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if(rx_pointer[4])
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rx_sample[79:64] <= rx_word[15:0];
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if(rx_pointer[5])
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rx_sample[95:80] <= rx_word[15:0];
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if(rx_pointer[6])
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rx_sample[111:96] <= rx_word[15:0];
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end // if (rx_frame)
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//#####################
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//#DATA VALID SIGNAL
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//####################
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always @ (posedge rx_lclk)
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access <= rx_pointer[6];
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always @ (posedge rx_lclk or negedge erx_io_nreset)
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if(!erx_io_nreset)
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burst_detect <= 1'b0;
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else if(access & rx_frame)
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burst_detect <= 1'b1;
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else if(~rx_frame)
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burst_detect <= 1'b0;
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//###################################
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//#SAMPLE AND HOLD DATA
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//###################################
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//(..and shuffle data for 104 bit packet)
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//seems redundant??? for burst??
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always @ (posedge rx_lclk or negedge erx_io_nreset)
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if(~erx_io_nreset)
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burst <= 1'b0;
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else if (access)
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burst <= burst_detect;
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always @ (posedge rx_lclk)
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if(access)
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begin
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//access
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rx_packet_lclk[0] <= rx_sample[40];
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//write
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rx_packet_lclk[1] <= rx_sample[41];
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//datamode
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rx_packet_lclk[3:2] <= rx_sample[43:42];
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//ctrlmode
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rx_packet_lclk[7:4] <= rx_sample[15:12];
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//dstaddr
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rx_packet_lclk[39:8] <= {rx_sample[11:8],
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rx_sample[23:16],
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rx_sample[31:24],
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rx_sample[39:32],
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rx_sample[47:44]};
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//data
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rx_packet_lclk[71:40] <= {rx_sample[55:48],
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rx_sample[63:56],
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rx_sample[71:64],
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rx_sample[79:72]};
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//srcaddr
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rx_packet_lclk[103:72]<= {rx_sample[87:80],
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rx_sample[95:88],
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rx_sample[103:96],
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rx_sample[111:104]
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};
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end
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//###################################
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//#SYNCHRONIZE TO SLOW CLK
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//###################################
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//stretch access pulse to 4 cycles
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//use shift register for speed
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always @ (posedge rx_lclk)
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if(!erx_io_nreset)
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valid[3:0] <=4'b0000;
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else if(access)
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valid[3:0] <=4'b1111;
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else
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valid[3:0] <={valid[2:0],1'b0};
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assign access_wide = valid[3];
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//clock handoff
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always @ (posedge rx_lclk_div4)
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begin
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rx_access <= access_wide;
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end
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always @ (posedge rx_lclk_div4)
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if(access_wide)
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begin
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rx_packet[PW-1:0] <= rx_packet_lclk[PW-1:0];
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rx_burst <= burst;
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end
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//################################
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//# I/O Buffers Instantiation
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//################################
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IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
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ibuf_data[7:0]
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(.I (rxi_data_p[7:0]),
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.IB (rxi_data_n[7:0]),
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.O (rxi_data[7:0]));
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IBUFDS #(.DIFF_TERM ("TRUE"), .IOSTANDARD (IOSTD_ELINK))
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ibuf_frame
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(.I (rxi_frame_p),
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.IB (rxi_frame_n),
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.O (rxi_frame));
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//TODO: Will this work?
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`ifdef TARGET_E64
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IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
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ibuf_lclk (.I (rxi_lclk_n),
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.IB (rxi_lclk_p),
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.O (rx_clkin)
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);
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`else
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IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
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ibuf_lclk (.I (rxi_lclk_p),
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.IB (rxi_lclk_n),
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.O (rx_clkin)
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);
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`endif
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generate
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if(ETYPE==1)
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begin
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OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
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obuft_wrwait (
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.O(rxo_wr_wait_p),
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.T(rx_wr_wait),
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.I(1'b0)
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);
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OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
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obuft_rdwait (
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.O(rxo_rd_wait_p),
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.T(rx_rd_wait),
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.I(1'b0)
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);
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assign rxo_wr_wait_n = 1'b0;
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assign rxo_rd_wait_n = 1'b0;
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end
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else if(ETYPE==0)
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begin
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OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
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obufds_wrwait (
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.O(rxo_wr_wait_p),
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.OB(rxo_wr_wait_n),
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.I(rx_wr_wait ^ invert_pins)
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);
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OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
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obufds_rdwait (.O(rxo_rd_wait_p),
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.OB(rxo_rd_wait_n),
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.I(rx_rd_wait ^ invert_pins)
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);
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end
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endgenerate
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//###################################
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//#RX CLOCK for IDDR
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//###################################
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wire rx_lclk_iddr;
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BUFIO i_bufio0 (.I(rx_clkin), .O(rx_lclk_iddr));//for iddr
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//###################################
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//#IDELAY CIRCUIT
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//###################################
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assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
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genvar j;
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generate for(j=0; j<9; j=j+1)
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begin : gen_idelay
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(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
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IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
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.DELAY_SRC("IDATAIN"),
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.HIGH_PERFORMANCE_MODE("FALSE"),
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.IDELAY_TYPE("VAR_LOAD"),
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.IDELAY_VALUE(5'b0),
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.PIPE_SEL("FALSE"),
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.REFCLK_FREQUENCY(200.0),
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.SIGNAL_PATTERN("DATA"))
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idelay_inst (.CNTVALUEOUT(), // monitoring value
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.DATAOUT(rxi_delay_out[j]), // delayed data
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.C(rx_lclk_div4), // variable tap delay clock
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.CE(1'b0), // inc/dec tap value
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.CINVCTRL(1'b0), // inverts clock polarity
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.CNTVALUEIN(idelay_value[(j+1)*5-1:j*5]), //variable tap
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.DATAIN(1'b0), // data from FPGA
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.IDATAIN(rxi_delay_in[j]), // data from ibuf
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.INC(1'b0), // increment tap
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.LD(load_taps), // load new
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.LDPIPEEN(1'b0), // only for pipeline mode
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.REGRST(1'b0) // only for pipeline mode
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);
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end // block: gen_idelay
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endgenerate
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//#############################
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//# IDDR SAMPLERS
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//#############################
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//DATA
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genvar i;
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generate for(i=0; i<8; i=i+1)
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begin : gen_iddr
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IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
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iddr_data (
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.Q1 (rx_word_iddr[i]),
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.Q2 (rx_word_iddr[i+8]),
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.C (rx_lclk_iddr),//rx_lclk_iddr
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.CE (1'b1),
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.D (rxi_delay_out[i] ^ invert_pins),
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.R (1'b0),
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.S (1'b0)
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);
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end
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endgenerate
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//FRAME
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IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
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iddr_frame (
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.Q1 (rx_frame_iddr),
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.Q2 (),
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.C (rx_lclk_iddr),//TODO: will this work?
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.CE (1'b1),
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.D (rxi_delay_out[8] ^ invert_pins),
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.R (1'b0),
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.S (1'b0)
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);
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endmodule // erx_io
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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