mirror of
https://github.com/aolofsson/oh.git
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251 lines
8.0 KiB
Verilog
251 lines
8.0 KiB
Verilog
/*
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########################################################################
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ELINK TX CONFIGURATION REGISTER FILE
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########################################################################
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*/
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`include "elink_regmap.v"
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module etx_cfg (/*AUTOARG*/
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// Outputs
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cfg_mmu_access, etx_cfg_access, etx_cfg_packet, tx_enable,
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mmu_enable, gpio_enable, remap_enable, burst_enable, gpio_data,
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ctrlmode, ctrlmode_bypass,
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// Inputs
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nreset, clk, cfg_access, etx_access, etx_packet, etx_wait,
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tx_status
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);
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//##################################################################
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//# INTERFACE
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//##################################################################
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parameter AW = 32;
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parameter PW = 2*AW+40;
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parameter RFAW = 6;
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parameter VERSION = 16'h0000;
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parameter ID = 999;
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//reset+clk
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input nreset; // sync reset
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input clk; // slow clock
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//packet input
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input cfg_access; // register access
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input etx_access; // for transaction counter
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input [PW-1:0] etx_packet; // for transaction sampler
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input etx_wait; // wait signal
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output cfg_mmu_access; // mmu access
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//packet output (for RX)
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output etx_cfg_access; // access for rx (write or rdata forward)
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output [PW-1:0] etx_cfg_packet; // packet
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//tx (static configs)
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output tx_enable; // enable signal for TX
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output mmu_enable; // enables MMU on transmit path
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output gpio_enable; // forces TX output pins to constants
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output remap_enable; // enable address remapping
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output burst_enable; // enables bursting
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output [8:0] gpio_data; // data for elink outputs (static)
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output [3:0] ctrlmode; // value for emesh ctrlmode tag
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output ctrlmode_bypass; // selects ctrlmode
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input [15:0] tx_status; // tx status signals
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//##################################################################
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//# BODY
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//##################################################################
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//registers/wires
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reg [15:0] tx_version_reg;
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reg [11:0] tx_cfg_reg;
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reg [8:0] tx_gpio_reg;
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reg [15:0] tx_status_reg;
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reg [31:0] tx_monitor_reg;
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reg [31:0] tx_packet_reg;
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reg [31:0] cfg_dout;
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reg ecfg_access;
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reg [1:0] datamode_out;
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reg [4:0] ctrlmode_out;
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reg write_out;
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reg [AW-1:0] dstaddr_out;
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reg [AW-1:0] srcaddr_out;
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reg [AW-1:0] data_out;
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reg read_sel;
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reg etx_cfg_access;
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wire [15:0] tx_status_sync;
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wire [31:0] data_mux;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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//###########################
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//# DECODE LOGIC
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//###########################
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packet2emesh #(.AW(AW))
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p2e (.packet_in (etx_packet[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]));
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//read/write decode
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assign tx_match = cfg_access &
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(dstaddr_in[19:16] ==`EGROUP_MMR) &
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(dstaddr_in[10:8] ==`EGROUP_TX);
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//MMU access
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assign cfg_mmu_access = cfg_access &
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(dstaddr_in[19:16] ==`EGROUP_MMU) &
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~dstaddr_in[15];
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assign ecfg_read = tx_match & ~write_in;
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assign ecfg_write = tx_match & write_in;
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//Config write enables
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assign tx_version_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`E_VERSION);
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assign tx_cfg_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ETX_CFG);
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assign tx_status_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ETX_STATUS);
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assign tx_gpio_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ETX_GPIO);
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assign tx_monitor_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ETX_MONITOR);
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//###########################
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//# TX CONFIG
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//###########################
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always @ (posedge clk)
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if(!nreset)
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tx_cfg_reg[11:0] <= 'b0;
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else if (tx_cfg_write)
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tx_cfg_reg[11:0] <= data_in[11:0];
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assign tx_enable = 1'b1;//TODO: fix! ecfg_tx_config_reg[0];
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assign mmu_enable = tx_cfg_reg[1];
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assign remap_enable = (tx_cfg_reg[3:2]==2'b01);
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assign ctrlmode[3:0] = tx_cfg_reg[7:4];
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assign ctrlmode_bypass = tx_cfg_reg[9];
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assign burst_enable = tx_cfg_reg[10];
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assign gpio_enable = (tx_cfg_reg[11:10]==2'b01);
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//###########################
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//# STATUS REGISTER
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//###########################
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//Synchronize to make easy regular
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oh_dsync #(.DW(16))
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dsync (// Outputs
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.dout (tx_status_sync[15:0]),
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// Inputs
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.clk (clk),
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.din (tx_status[15:0])
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);
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always @ (posedge clk)
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if (tx_status_write)
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tx_status_reg[15:0] <= data_in[15:0];
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else
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tx_status_reg[15:0]<= tx_status_reg[15:0] | {tx_status_sync[15:0]};
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//###########################
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//# GPIO DATA
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//###########################
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always @ (posedge clk)
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if (tx_gpio_write)
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tx_gpio_reg[8:0] <= data_in[8:0];
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assign gpio_data[8:0] = tx_gpio_reg[8:0];
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//###########################
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//# VERSION
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//###########################
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always @ (posedge clk)
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if(!nreset)
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tx_version_reg[15:0] <= VERSION;
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else if (tx_version_write)
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tx_version_reg[15:0] <= data_in[15:0];
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//###########################
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//# MONITOR
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//###########################
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always @ (posedge clk)
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if (tx_monitor_write)
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tx_monitor_reg[31:0] <= data_in[31:0];
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else
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tx_monitor_reg[31:0] <= tx_monitor_reg[31:0] + (etx_access & ~etx_wait);
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//###########################
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//# PACKET (FOR DEBUG)
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//###########################
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always @ (posedge clk)
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if(etx_access)
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tx_packet_reg[31:0] <= etx_packet[39:8];
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//###############################
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//# DATA READBACK MUX
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//###############################
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//Pipelineing readback
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always @ (posedge clk)
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if(ecfg_read)
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case(dstaddr_in[RFAW+1:2])
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`E_VERSION: cfg_dout[31:0] <= {16'b0, tx_version_reg[15:0]};
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`ETX_CFG: cfg_dout[31:0] <= {21'b0, tx_cfg_reg[10:0]};
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`ETX_GPIO: cfg_dout[31:0] <= {23'b0, tx_gpio_reg[8:0]};
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`ETX_STATUS: cfg_dout[31:0] <= {16'b0, tx_status_reg[15:0]};
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`ETX_MONITOR: cfg_dout[31:0] <= {tx_monitor_reg[31:0]};
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`ETX_PACKET: cfg_dout[31:0] <= {tx_packet_reg[31:0]};
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default: cfg_dout[31:0] <= 32'd0;
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endcase // case (dstaddr_in[RFAW+1:2])
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else
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cfg_dout[31:0] <= 32'd0;
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//###########################
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//# FORWARD PACKET TO RX
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//###########################
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//pipeline
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always @ (posedge clk)
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if(~etx_wait)
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begin
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etx_cfg_access <= cfg_access;
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datamode_out[1:0] <= datamode_in[1:0];
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ctrlmode_out[4:0] <= {1'b0,ctrlmode_in[3:0]};
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write_out <= ecfg_read | write_in;
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dstaddr_out[31:0] <= ecfg_read ? srcaddr_in[31:0] : dstaddr_in[31:0];
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data_out[31:0] <= data_in[31:0];
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srcaddr_out[31:0] <= srcaddr_in[31:0];
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read_sel <= ecfg_read;
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end
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assign data_mux[31:0] = read_sel ? cfg_dout[31:0] :
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data_out[31:0];
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//Create packet
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emesh2packet #(.AW(AW))
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e2p (.packet_out (etx_cfg_packet[PW-1:0]),
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.data_out (data_mux[AW-1:0]),
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/*AUTOINST*/
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// Inputs
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.write_out (write_out),
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.datamode_out (datamode_out[1:0]),
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.ctrlmode_out (ctrlmode_out[4:0]),
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.dstaddr_out (dstaddr_out[AW-1:0]),
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.srcaddr_out (srcaddr_out[AW-1:0]));
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endmodule // ecfg_tx
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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