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77 lines
1.8 KiB
Verilog
77 lines
1.8 KiB
Verilog
module etx_remap (/*AUTOARG*/
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// Outputs
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emesh_access_out, emesh_packet_out,
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// Inputs
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clk, nreset, emesh_access_in, emesh_packet_in, remap_en, etx_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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//Clock
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input clk;
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input nreset;
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//Input from arbiter
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input emesh_access_in;
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input [PW-1:0] emesh_packet_in;
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input remap_en; //enable tx remap (static)
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//Output to TX IO
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output emesh_access_out;
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output [PW-1:0] emesh_packet_out;
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//Wait signals from protocol block
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input etx_wait;
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wire [31:0] addr_in;
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wire [31:0] addr_remap;
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wire [31:0] addr_out;
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wire write_in;
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reg emesh_access_out;
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reg [PW-1:0] emesh_packet_out;
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packet2emesh #(.AW(AW))
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p2e (// Outputs
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.write_in (write_in),
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.datamode_in (),
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.ctrlmode_in (),
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.data_in (),
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.dstaddr_in (addr_in[31:0]),
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.srcaddr_in (),
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// Inputs
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.packet_in (emesh_packet_in[PW-1:0]));
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assign addr_remap[31:0] = {addr_in[29:18], //ID
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addr_in[17:16], //SPECIAL GROUP
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{(2){(|addr_in[17:16])}},//ZERO IF NOT SPECIAL
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addr_in[15:0]
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};
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assign addr_out[31:0] = remap_en ? addr_remap[31:0] :
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addr_in[31:0];
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//stall read/write access appropriately
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always @ (posedge clk)
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if(!nreset)
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emesh_access_out <= 1'b0;
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else if(~etx_wait)
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emesh_access_out <= emesh_access_in;
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always @ (posedge clk)
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if(~etx_wait)
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emesh_packet_out[PW-1:0] <= {emesh_packet_in[PW-1:40],
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addr_out[31:0],
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emesh_packet_in[7:0]
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};
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endmodule // etx_remap
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl")
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// End:
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