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30 lines
551 B
Verilog
30 lines
551 B
Verilog
//MEMORY MAP
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//Group set with bits 19:16
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//Epiphany Register Memory Map
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`define EGROUP_MMR 4'hF
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`define EGROUP_RXMMU 4'hE
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`define EGROUP_TXMMU 4'hD
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`define EGROUP_EMBOX 4'hC
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//ELINK REGISTERS addr[6:2]
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`define ESYSRESET 5'h0
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`define ESYSTX 5'h1
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`define ESYSRX 5'h2
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`define ESYSCLK 5'h3
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`define ESYSCOREID 5'h4
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`define ESYSVERSION 5'h5
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`define ESYSDATAIN 5'h6
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`define ESYSDATAOUT 5'h7
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`define ESYSDEBUG 5'h8
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//MESSAGE BOX
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`define EMBOXLO 5'h0
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`define EMBOXHI 5'h1
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//RX MMU addr[15:0]
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//TX MMU addr[15:0]
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