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abd25426b6
-sandbox accelerator working in simulation! -t0+6 hrs wall time (lost 2 hours due to travel)
347 lines
15 KiB
Verilog
347 lines
15 KiB
Verilog
`include "elink_regmap.v"
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module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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// Inputs
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clk, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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//##########################################################################
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//# INTERFACE
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//##########################################################################
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parameter AW = 32;
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parameter ID = 12'h810;
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parameter S_IDW = 12;
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parameter M_IDW = 6;
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parameter PW = 2*AW + 40;
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parameter N = 1;
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//clock,reset
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input clk;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transaction
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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//##########################################################################
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//#BODY
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//##########################################################################
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wire mem_rd_wait;
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wire mem_wr_wait;
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wire mem_access;
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wire [PW-1:0] mem_packet;
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/*AUTOINPUT*/
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire irq; // From axi_accelerator of axi_accelerator.v
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wire [31:0] m_axi_araddr; // From axi_accelerator of axi_accelerator.v
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wire [1:0] m_axi_arburst; // From axi_accelerator of axi_accelerator.v
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wire [3:0] m_axi_arcache; // From axi_accelerator of axi_accelerator.v
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wire [M_IDW-1:0] m_axi_arid; // From axi_accelerator of axi_accelerator.v
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wire [7:0] m_axi_arlen; // From axi_accelerator of axi_accelerator.v
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wire m_axi_arlock; // From axi_accelerator of axi_accelerator.v
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wire [2:0] m_axi_arprot; // From axi_accelerator of axi_accelerator.v
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wire [3:0] m_axi_arqos; // From axi_accelerator of axi_accelerator.v
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wire m_axi_arready; // From m_stub of axislave_stub.v
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wire [2:0] m_axi_arsize; // From axi_accelerator of axi_accelerator.v
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wire m_axi_arvalid; // From axi_accelerator of axi_accelerator.v
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wire [31:0] m_axi_awaddr; // From axi_accelerator of axi_accelerator.v
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wire [1:0] m_axi_awburst; // From axi_accelerator of axi_accelerator.v
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wire [3:0] m_axi_awcache; // From axi_accelerator of axi_accelerator.v
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wire [M_IDW-1:0] m_axi_awid; // From axi_accelerator of axi_accelerator.v
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wire [7:0] m_axi_awlen; // From axi_accelerator of axi_accelerator.v
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wire m_axi_awlock; // From axi_accelerator of axi_accelerator.v
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wire [2:0] m_axi_awprot; // From axi_accelerator of axi_accelerator.v
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wire [3:0] m_axi_awqos; // From axi_accelerator of axi_accelerator.v
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wire m_axi_awready; // From m_stub of axislave_stub.v
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wire [2:0] m_axi_awsize; // From axi_accelerator of axi_accelerator.v
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wire m_axi_awvalid; // From axi_accelerator of axi_accelerator.v
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wire [S_IDW-1:0] m_axi_bid; // From m_stub of axislave_stub.v
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wire m_axi_bready; // From axi_accelerator of axi_accelerator.v
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wire [1:0] m_axi_bresp; // From m_stub of axislave_stub.v
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wire m_axi_bvalid; // From m_stub of axislave_stub.v
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wire [31:0] m_axi_rdata; // From m_stub of axislave_stub.v
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wire [S_IDW-1:0] m_axi_rid; // From m_stub of axislave_stub.v
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wire m_axi_rlast; // From m_stub of axislave_stub.v
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wire m_axi_rready; // From axi_accelerator of axi_accelerator.v
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wire [1:0] m_axi_rresp; // From m_stub of axislave_stub.v
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wire m_axi_rvalid; // From m_stub of axislave_stub.v
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wire [63:0] m_axi_wdata; // From axi_accelerator of axi_accelerator.v
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wire [M_IDW-1:0] m_axi_wid; // From axi_accelerator of axi_accelerator.v
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wire m_axi_wlast; // From axi_accelerator of axi_accelerator.v
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wire m_axi_wready; // From m_stub of axislave_stub.v
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wire [7:0] m_axi_wstrb; // From axi_accelerator of axi_accelerator.v
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wire m_axi_wvalid; // From axi_accelerator of axi_accelerator.v
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wire [31:0] s_axi_araddr; // From emaxi of emaxi.v
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wire [1:0] s_axi_arburst; // From emaxi of emaxi.v
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wire [3:0] s_axi_arcache; // From emaxi of emaxi.v
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wire [M_IDW-1:0] s_axi_arid; // From emaxi of emaxi.v
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wire [7:0] s_axi_arlen; // From emaxi of emaxi.v
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wire s_axi_arlock; // From emaxi of emaxi.v
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wire [2:0] s_axi_arprot; // From emaxi of emaxi.v
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wire [3:0] s_axi_arqos; // From emaxi of emaxi.v
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wire s_axi_arready; // From axi_accelerator of axi_accelerator.v
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wire [2:0] s_axi_arsize; // From emaxi of emaxi.v
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wire s_axi_arvalid; // From emaxi of emaxi.v
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wire [31:0] s_axi_awaddr; // From emaxi of emaxi.v
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wire [1:0] s_axi_awburst; // From emaxi of emaxi.v
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wire [3:0] s_axi_awcache; // From emaxi of emaxi.v
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wire [M_IDW-1:0] s_axi_awid; // From emaxi of emaxi.v
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wire [7:0] s_axi_awlen; // From emaxi of emaxi.v
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wire s_axi_awlock; // From emaxi of emaxi.v
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wire [2:0] s_axi_awprot; // From emaxi of emaxi.v
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wire [3:0] s_axi_awqos; // From emaxi of emaxi.v
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wire s_axi_awready; // From axi_accelerator of axi_accelerator.v
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wire [2:0] s_axi_awsize; // From emaxi of emaxi.v
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wire s_axi_awvalid; // From emaxi of emaxi.v
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wire [S_IDW-1:0] s_axi_bid; // From axi_accelerator of axi_accelerator.v
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wire s_axi_bready; // From emaxi of emaxi.v
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wire [1:0] s_axi_bresp; // From axi_accelerator of axi_accelerator.v
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wire s_axi_bvalid; // From axi_accelerator of axi_accelerator.v
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wire [31:0] s_axi_rdata; // From axi_accelerator of axi_accelerator.v
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wire [S_IDW-1:0] s_axi_rid; // From axi_accelerator of axi_accelerator.v
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wire s_axi_rlast; // From axi_accelerator of axi_accelerator.v
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wire s_axi_rready; // From emaxi of emaxi.v
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wire [1:0] s_axi_rresp; // From axi_accelerator of axi_accelerator.v
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wire s_axi_rvalid; // From axi_accelerator of axi_accelerator.v
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wire [63:0] s_axi_wdata; // From emaxi of emaxi.v
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wire [M_IDW-1:0] s_axi_wid; // From emaxi of emaxi.v
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wire s_axi_wlast; // From emaxi of emaxi.v
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wire s_axi_wready; // From axi_accelerator of axi_accelerator.v
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wire [7:0] s_axi_wstrb; // From emaxi of emaxi.v
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wire s_axi_wvalid; // From emaxi of emaxi.v
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// End of automatics
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//######################################################################
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//ACCELERATOR
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//######################################################################
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axi_accelerator
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axi_accelerator (.sys_nreset (nreset),
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.sys_clk (clk),
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.m_axi_aresetn (nreset),
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.s_axi_aresetn (nreset),
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.s_axi_wstrb (s_axi_wstrb[7:4] | s_axi_wstrb[3:0]),
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/*AUTOINST*/
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// Outputs
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.irq (irq),
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.m_axi_awid (m_axi_awid[M_IDW-1:0]),
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.m_axi_awaddr (m_axi_awaddr[31:0]),
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.m_axi_awlen (m_axi_awlen[7:0]),
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.m_axi_awsize (m_axi_awsize[2:0]),
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.m_axi_awburst (m_axi_awburst[1:0]),
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.m_axi_awlock (m_axi_awlock),
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.m_axi_awcache (m_axi_awcache[3:0]),
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.m_axi_awprot (m_axi_awprot[2:0]),
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.m_axi_awqos (m_axi_awqos[3:0]),
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.m_axi_awvalid (m_axi_awvalid),
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.m_axi_wid (m_axi_wid[M_IDW-1:0]),
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.m_axi_wdata (m_axi_wdata[63:0]),
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.m_axi_wstrb (m_axi_wstrb[7:0]),
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.m_axi_wlast (m_axi_wlast),
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.m_axi_wvalid (m_axi_wvalid),
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.m_axi_bready (m_axi_bready),
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.m_axi_arid (m_axi_arid[M_IDW-1:0]),
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.m_axi_araddr (m_axi_araddr[31:0]),
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.m_axi_arlen (m_axi_arlen[7:0]),
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.m_axi_arsize (m_axi_arsize[2:0]),
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.m_axi_arburst (m_axi_arburst[1:0]),
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.m_axi_arlock (m_axi_arlock),
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.m_axi_arcache (m_axi_arcache[3:0]),
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.m_axi_arprot (m_axi_arprot[2:0]),
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.m_axi_arqos (m_axi_arqos[3:0]),
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.m_axi_arvalid (m_axi_arvalid),
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.m_axi_rready (m_axi_rready),
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.s_axi_arready (s_axi_arready),
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.s_axi_awready (s_axi_awready),
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.s_axi_bid (s_axi_bid[S_IDW-1:0]),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_rid (s_axi_rid[S_IDW-1:0]),
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.s_axi_rdata (s_axi_rdata[31:0]),
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.s_axi_rlast (s_axi_rlast),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_wready (s_axi_wready),
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// Inputs
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.m_axi_awready (m_axi_awready),
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.m_axi_wready (m_axi_wready),
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.m_axi_bid (m_axi_bid[M_IDW-1:0]),
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.m_axi_bresp (m_axi_bresp[1:0]),
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.m_axi_bvalid (m_axi_bvalid),
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.m_axi_arready (m_axi_arready),
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.m_axi_rid (m_axi_rid[M_IDW-1:0]),
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.m_axi_rdata (m_axi_rdata[63:0]),
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.m_axi_rresp (m_axi_rresp[1:0]),
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.m_axi_rlast (m_axi_rlast),
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.m_axi_rvalid (m_axi_rvalid),
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.s_axi_arid (s_axi_arid[S_IDW-1:0]),
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.s_axi_araddr (s_axi_araddr[31:0]),
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.s_axi_arburst (s_axi_arburst[1:0]),
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.s_axi_arcache (s_axi_arcache[3:0]),
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.s_axi_arlock (s_axi_arlock),
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.s_axi_arlen (s_axi_arlen[7:0]),
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.s_axi_arprot (s_axi_arprot[2:0]),
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.s_axi_arqos (s_axi_arqos[3:0]),
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.s_axi_arsize (s_axi_arsize[2:0]),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_awid (s_axi_awid[S_IDW-1:0]),
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.s_axi_awaddr (s_axi_awaddr[31:0]),
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.s_axi_awburst (s_axi_awburst[1:0]),
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.s_axi_awcache (s_axi_awcache[3:0]),
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.s_axi_awlock (s_axi_awlock),
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.s_axi_awlen (s_axi_awlen[7:0]),
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.s_axi_awprot (s_axi_awprot[2:0]),
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.s_axi_awqos (s_axi_awqos[3:0]),
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.s_axi_awsize (s_axi_awsize[2:0]),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_rready (s_axi_rready),
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.s_axi_wid (s_axi_wid[S_IDW-1:0]),
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.s_axi_wdata (s_axi_wdata[31:0]),
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.s_axi_wlast (s_axi_wlast),
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.s_axi_wvalid (s_axi_wvalid));
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//######################################################################
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//AXI MASTER
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//######################################################################
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//Split stimulus to read/write
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assign wait_out = wr_wait | rd_wait;
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assign write_in = access_in & packet_in[0];
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assign read_in = access_in & ~packet_in[0];
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/*emaxi AUTO_TEMPLATE (.m_\(.*\) (s_\1[]),
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);
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*/
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emaxi #(.M_IDW(M_IDW))
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emaxi (.m_axi_aclk (clk),
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.m_axi_aresetn (nreset),
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.m_axi_rdata ({s_axi_rdata[31:0],s_axi_rdata[31:0]}),
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.rr_wait (wait_in),
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.rr_access (access_out),
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.rr_packet (packet_out[PW-1:0]),
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.wr_wait (wr_wait),
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.wr_access (write_in),
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.wr_packet (packet_in[PW-1:0]),
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.rd_wait (rd_wait),
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.rd_access (read_in),
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.rd_packet (packet_in[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.m_axi_awid (s_axi_awid[M_IDW-1:0]), // Templated
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.m_axi_awaddr (s_axi_awaddr[31:0]), // Templated
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.m_axi_awlen (s_axi_awlen[7:0]), // Templated
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.m_axi_awsize (s_axi_awsize[2:0]), // Templated
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.m_axi_awburst (s_axi_awburst[1:0]), // Templated
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.m_axi_awlock (s_axi_awlock), // Templated
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.m_axi_awcache (s_axi_awcache[3:0]), // Templated
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.m_axi_awprot (s_axi_awprot[2:0]), // Templated
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.m_axi_awqos (s_axi_awqos[3:0]), // Templated
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.m_axi_awvalid (s_axi_awvalid), // Templated
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.m_axi_wid (s_axi_wid[M_IDW-1:0]), // Templated
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.m_axi_wdata (s_axi_wdata[63:0]), // Templated
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.m_axi_wstrb (s_axi_wstrb[7:0]), // Templated
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.m_axi_wlast (s_axi_wlast), // Templated
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.m_axi_wvalid (s_axi_wvalid), // Templated
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.m_axi_bready (s_axi_bready), // Templated
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.m_axi_arid (s_axi_arid[M_IDW-1:0]), // Templated
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.m_axi_araddr (s_axi_araddr[31:0]), // Templated
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.m_axi_arlen (s_axi_arlen[7:0]), // Templated
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.m_axi_arsize (s_axi_arsize[2:0]), // Templated
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.m_axi_arburst (s_axi_arburst[1:0]), // Templated
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.m_axi_arlock (s_axi_arlock), // Templated
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.m_axi_arcache (s_axi_arcache[3:0]), // Templated
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.m_axi_arprot (s_axi_arprot[2:0]), // Templated
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.m_axi_arqos (s_axi_arqos[3:0]), // Templated
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.m_axi_arvalid (s_axi_arvalid), // Templated
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.m_axi_rready (s_axi_rready), // Templated
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// Inputs
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.m_axi_awready (s_axi_awready), // Templated
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.m_axi_wready (s_axi_wready), // Templated
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.m_axi_bid (s_axi_bid[M_IDW-1:0]), // Templated
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.m_axi_bresp (s_axi_bresp[1:0]), // Templated
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.m_axi_bvalid (s_axi_bvalid), // Templated
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.m_axi_arready (s_axi_arready), // Templated
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.m_axi_rid (s_axi_rid[M_IDW-1:0]), // Templated
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.m_axi_rresp (s_axi_rresp[1:0]), // Templated
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.m_axi_rlast (s_axi_rlast), // Templated
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.m_axi_rvalid (s_axi_rvalid)); // Templated
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assign dut_active = 1'b1;
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//Tie off master output for now
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/*axislave_stub AUTO_TEMPLATE (.s_\(.*\) (m_\1[]),
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);
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*/
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axislave_stub m_stub (.s_axi_aclk (clk),
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.s_axi_aresetn (nreset),
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/*AUTOINST*/
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// Outputs
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.s_axi_arready (m_axi_arready), // Templated
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.s_axi_awready (m_axi_awready), // Templated
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.s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated
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.s_axi_bresp (m_axi_bresp[1:0]), // Templated
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.s_axi_bvalid (m_axi_bvalid), // Templated
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.s_axi_rid (m_axi_rid[S_IDW-1:0]), // Templated
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.s_axi_rdata (m_axi_rdata[31:0]), // Templated
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.s_axi_rlast (m_axi_rlast), // Templated
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.s_axi_rresp (m_axi_rresp[1:0]), // Templated
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.s_axi_rvalid (m_axi_rvalid), // Templated
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.s_axi_wready (m_axi_wready), // Templated
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// Inputs
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.s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated
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.s_axi_araddr (m_axi_araddr[31:0]), // Templated
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.s_axi_arburst (m_axi_arburst[1:0]), // Templated
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.s_axi_arcache (m_axi_arcache[3:0]), // Templated
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.s_axi_arlock (m_axi_arlock), // Templated
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.s_axi_arlen (m_axi_arlen[7:0]), // Templated
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.s_axi_arprot (m_axi_arprot[2:0]), // Templated
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.s_axi_arqos (m_axi_arqos[3:0]), // Templated
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.s_axi_arsize (m_axi_arsize[2:0]), // Templated
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.s_axi_arvalid (m_axi_arvalid), // Templated
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.s_axi_awid (m_axi_awid[S_IDW-1:0]), // Templated
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.s_axi_awaddr (m_axi_awaddr[31:0]), // Templated
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.s_axi_awburst (m_axi_awburst[1:0]), // Templated
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.s_axi_awcache (m_axi_awcache[3:0]), // Templated
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.s_axi_awlock (m_axi_awlock), // Templated
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.s_axi_awlen (m_axi_awlen[7:0]), // Templated
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.s_axi_awprot (m_axi_awprot[2:0]), // Templated
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.s_axi_awqos (m_axi_awqos[3:0]), // Templated
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.s_axi_awsize (m_axi_awsize[2:0]), // Templated
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.s_axi_awvalid (m_axi_awvalid), // Templated
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.s_axi_bready (m_axi_bready), // Templated
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.s_axi_rready (m_axi_rready), // Templated
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.s_axi_wid (m_axi_wid[S_IDW-1:0]), // Templated
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.s_axi_wdata (m_axi_wdata[31:0]), // Templated
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.s_axi_wlast (m_axi_wlast), // Templated
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.s_axi_wstrb (m_axi_wstrb[3:0]), // Templated
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.s_axi_wvalid (m_axi_wvalid)); // Templated
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endmodule
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../axi/dv" "../../emesh/hdl" "../../memory/hdl" "../../axi/hdl")
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// End:
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