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86 lines
2.3 KiB
Verilog
86 lines
2.3 KiB
Verilog
/*
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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`timescale 1ns / 1ps
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module test_aes_128;
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// Inputs
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reg clk;
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reg [127:0] state;
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reg [127:0] key;
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// Outputs
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wire [127:0] out;
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// Instantiate the Unit Under Test (UUT)
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aes_128 uut (
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.clk(clk),
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.state(state),
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.key(key),
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.out(out)
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);
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initial begin
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clk = 0;
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state = 0;
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key = 0;
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#100;
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/*
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* TIMEGRP "key" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
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* TIMEGRP "state" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
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* TIMEGRP "out" OFFSET = OUT 2.2 ns BEFORE "clk" HIGH;
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*/
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@ (negedge clk);
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# 2;
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state = 128'h3243f6a8_885a308d_313198a2_e0370734;
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key = 128'h2b7e1516_28aed2a6_abf71588_09cf4f3c;
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#10;
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state = 128'h00112233_44556677_8899aabb_ccddeeff;
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key = 128'h00010203_04050607_08090a0b_0c0d0e0f;
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#10;
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state = 128'h0;
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key = 128'h0;
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#10;
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state = 128'h0;
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key = 128'h1;
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#10;
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state = 128'h1;
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key = 128'h0;
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#170;
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if (out !== 128'h3925841d02dc09fbdc118597196a0b32)
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begin $display("E"); $finish; end
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#10;
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if (out !== 128'h69_c4_e0_d8_6a_7b_04_30_d8_cd_b7_80_70_b4_c5_5a)
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begin $display("E"); $finish; end
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#10;
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if (out !== 128'h66_e9_4b_d4_ef_8a_2c_3b_88_4c_fa_59_ca_34_2b_2e)
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begin $display("E"); $finish; end
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#10;
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if (out !== 128'h05_45_aa_d5_6d_a2_a9_7c_36_63_d1_43_2a_3d_1c_84)
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begin $display("E"); $finish; end
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#10;
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if (out !== 128'h58_e2_fc_ce_fa_7e_30_61_36_7f_1d_57_a4_e7_45_5a)
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begin $display("E"); $finish; end
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$display("Good.");
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$finish;
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end
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always #5 clk = ~clk;
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endmodule
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