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58 lines
1.4 KiB
Verilog
58 lines
1.4 KiB
Verilog
/*
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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`timescale 1ns / 1ps
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module test_table_lookup;
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// Inputs
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reg clk;
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reg [31:0] state;
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// Outputs
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wire [31:0] p0;
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wire [31:0] p1;
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wire [31:0] p2;
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wire [31:0] p3;
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// Instantiate the Unit Under Test (UUT)
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table_lookup uut (
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.clk(clk),
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.state(state),
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.p0(p0),
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.p1(p1),
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.p2(p2),
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.p3(p3)
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);
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initial begin
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clk = 0;
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state = 0;
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#100;
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state = 31'h193de3be;
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#10;
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if (p0 !== 32'hb3_d4_d4_67) begin $display("E"); $finish; end
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if (p1 !== 32'h69_4e_27_27) begin $display("E"); $finish; end
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if (p2 !== 32'h11_33_22_11) begin $display("E"); $finish; end
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if (p3 !== 32'hae_ae_e9_47) begin $display("E"); $finish; end
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$display("Good.");
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$finish;
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end
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always #5 clk = ~clk;
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endmodule
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