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136 lines
4.2 KiB
Verilog
136 lines
4.2 KiB
Verilog
`include "spi_regmap.v"
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module spi_regs (/*AUTOARG*/
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// Outputs
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reg_rdata, cpol, cpha, txdata,
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// Inputs
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nreset, clk, reg_access, reg_packet, rxdata
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);
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//##################################################################
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//# INTERFACE
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//##################################################################
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parameter AW = 32; // data width of fifo
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parameter PW = 2*AW+40; // packet size
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parameter DEPTH = 32; // fifo depth
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//clk+reset
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input nreset; // asynchronous active low reset
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input clk; // write clock
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//register access
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input reg_access; // register access (read only)
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input [PW-1:0] reg_packet; // data/address
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output [31:0] reg_rdata; // readback data
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//controls
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output cpol;
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output cpha;
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//io interface
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output [7:0] txdata; // data in txfifo
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input [7:0] rxdata; // data for rxfifo
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//##################################################################
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//# BODY
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//##################################################################
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reg [31:0] status_reg;
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reg [31:0] cfg_reg;
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reg [31:0] ilat_reg;
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reg [31:0] imask_reg;
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reg [31:0] delay_reg;
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reg [31:0] tx_reg;
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reg [31:0] rx_reg;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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//################################
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//# REGISTER ACCESS DECODE
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//################################
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packet2emesh p2e(.packet_in (reg_packet[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]));
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assign reg_write = reg_access & write_in;
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assign reg_read = reg_access & ~write_in;
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assign cfg_write = reg_write & (dstaddr_in[7:2]==`SPI_CFG);
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assign status_write = reg_write & (dstaddr_in[7:2]==`SPI_STATUS);
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assign ilat_write = reg_write & (dstaddr_in[7:2]==`SPI_ILAT);
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assign imask_write = reg_write & (dstaddr_in[7:2]==`SPI_IMASK);
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assign delay_write = reg_write & (dstaddr_in[7:2]==`SPI_DELAY);
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assign tx_write = reg_write & (dstaddr_in[7:2]==`SPI_TX);
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////////////////////////
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//CFG
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always @ (posedge clk)
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if(cfg_write)
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cfg_reg[31:0] <= data_in[31:0];
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assign spi_en = cfg_reg[1];
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assign cpol = cfg_reg[2];
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assign cpha = cfg_reg[3];
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assign master_mode = cfg_reg[4];
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assign manual_mode = cfg_reg[5]; //
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assign irqen = cfg_reg[6]; //enable spi interrupt
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assign clkdiv[3:0] = cfg_reg[11:8];
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////////////////////////
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//STATUS
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always @ (posedge clk)
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if(status_write)
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status_reg[31:0] <= data_in[31:0];
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else
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status_reg[31:0] <= status_in[31:0];
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////////////////////////
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//ILAT
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always @ (posedge clk)
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if(status_write)
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status_reg[31:0] <= data_in[31:0];
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else
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status_reg[31:0] <= status_in[31:0];
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////////////////////////
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//IMASK
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always @ (posedge clk)
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if(status_write)
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//################################
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//# READBACK
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//################################
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always @ (posedge clk)
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if(reg_read)
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case(dstaddr_in[7:2])
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`SPI_CFG : reg_rdata[31:0] <= cfg_reg[31:0];
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`SPI_STATUS : reg_rdata[31:0] <= status_reg[31:0];
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`SPI_ILAT : reg_rdata[31:0] <= ilat_reg[31:0];
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`SPI_IMASK : reg_rdata[31:0] <= imask_reg[31:0];
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`SPI_DELAY : reg_rdata[31:0] <= delay_reg[31:0];
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`SPI_RX : reg_rdata[31:0] <= rx_reg[31:0];
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endcase // case (dstaddr_in[7:2])
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endmodule // spi_regs
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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