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231 lines
7.4 KiB
Verilog
231 lines
7.4 KiB
Verilog
//#############################################################################
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//# Purpose: SPI master (configurable) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see below) #
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//#############################################################################
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`include "spi_regmap.vh"
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module spi_master_regs (/*AUTOARG*/
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// Outputs
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cpol, cpha, lsbfirst, emode, spi_en, clkdiv_reg, cmd_reg, wait_out,
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access_out, packet_out,
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// Inputs
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clk, nreset, rx_data, rx_access, spi_state, fifo_prog_full,
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fifo_wait, access_in, packet_in, wait_in
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);
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//parameters
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parameter CLKDIV = 1; // default clkdiv
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parameter PSIZE = 0; // default is 32 bits
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parameter AW = 32; // addresss width
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localparam PW = (2*AW+40); // packet width
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//clk,reset, cfg
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input clk; // core clock
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input nreset; // async active low reset
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//io interface
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input [63:0] rx_data; // rx data
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input rx_access; // rx access pulse
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//control
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output cpol; // clk polarity (default is 0)
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output cpha; // clk phase shift (default is 0)
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output lsbfirst; // send lsbfirst
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output emode; // send emesh transaction
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output spi_en; // enable transmitter
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output [7:0] clkdiv_reg; // baud rate setting
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output [7:0] cmd_reg; // command register for emode
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input [1:0] spi_state; // transmit state
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input fifo_prog_full; // fifo reached half/full
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input fifo_wait; // tx transfer wait
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//packet to transmit
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input access_in; // access from core
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input [PW-1:0] packet_in; // data to core
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output wait_out; // pushback from spi master
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//return packet
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output access_out; // writeback from spi
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output [PW-1:0] packet_out; // writeback data from spi
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input wait_in; // pushback by core
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//########################################################
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//# BODY
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//########################################################
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reg [7:0] config_reg;
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reg [7:0] status_reg;
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reg [7:0] clkdiv_reg;
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reg [7:0] cmd_reg;
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reg [7:0] rx_reg[7:0];
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reg autotran;
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reg [31:0] read_data;
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reg access_out;
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integer i;
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wire [31:0] reg_wdata;
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wire [1:0] datamode_out;
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wire [AW-1:0] dstaddr_out;
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wire [AW-1:0] data_out;
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wire [AW-1:0] srcaddr_out;
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wire [4:0] ctrlmode_out;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] data_in; // From pe2 of packet2emesh.v
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wire [1:0] datamode_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From pe2 of packet2emesh.v
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wire write_in; // From pe2 of packet2emesh.v
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// End of automatics
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//####################################
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//# DECODE
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//####################################
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packet2emesh #(.AW(AW))
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pe2 (/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]),
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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assign reg_write = access_in & write_in;
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assign reg_read = access_in & ~write_in;
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assign reg_wdata[31:0] = data_in[AW-1:0];
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assign config_write = reg_write & (dstaddr_in[7:0]==`SPI_CONFIG);
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assign status_write = reg_write & (dstaddr_in[7:0]==`SPI_STATUS);
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assign clkdiv_write = reg_write & (dstaddr_in[7:0]==`SPI_CLKDIV);
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assign cmd_write = reg_write & (dstaddr_in[7:0]==`SPI_CMD);
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assign tx_write = reg_write & (dstaddr_in[7:0]==`SPI_TX);
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//####################################
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//# CONFIG
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//####################################
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always @ (posedge clk or negedge nreset)
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if (~nreset)
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config_reg[7:0] <= 'b0;
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else if(config_write)
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config_reg[7:0] <= data_in[7:0];
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assign spi_en = ~config_reg[0]; // disable spi (on by default)
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assign irq_en = config_reg[1]; // enable interrupt
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assign cpol = config_reg[2]; // cpol
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assign cpha = config_reg[3]; // cpha
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assign lsbfirst = config_reg[4]; // send lsb first
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assign manual_ss = config_reg[5]; // manually control ss pin
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assign emode = config_reg[6]; // epiphany transfer mode
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//####################################
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//# STATUS
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//####################################
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always @ (posedge clk or negedge nreset)
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if (~nreset)
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status_reg[7:0] <= 'b0;
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else if(status_write)
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status_reg[7:0] <= reg_wdata[7:0];
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else
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status_reg[7:0] <= {5'b0, //7:3
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fifo_prog_full, //2
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|spi_state[1:0], //1
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(rx_access | status_reg[0])};//0
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//####################################
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//# CLKDIV
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//####################################
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always @ (posedge clk or negedge nreset)
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if (~nreset)
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clkdiv_reg[7:0] <= CLKDIV;
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else if(clkdiv_write)
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clkdiv_reg[7:0] <= reg_wdata[7:0];
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//####################################
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//# COMMAND (for emode)
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//####################################
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always @ (posedge clk)
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if(cmd_write)
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cmd_reg[7:0] <= reg_wdata[7:0];
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//####################################
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//# RX REG
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//####################################
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always @ (posedge clk)
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if(rx_access)
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for(i=0;i<8;i=i+1)
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rx_reg[i] <= rx_data[i*8+:8];
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//####################################
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//# AUTOTRANSFER
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//####################################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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autotran <= 1'b0;
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else if(rx_access & emode)
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autotran <= 1'b1;
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else if(~wait_in)
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autotran <= 1'b0;
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//####################################
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//# READBACK
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//####################################
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always @ (posedge clk)
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access_out <= access_in;
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always @ (posedge clk)
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read_data[31:0] <= 64'b0;
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//create a pulse on register reads
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oh_edge2pulse
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e2pulse (.out (wait_pulse),
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.clk (clk),
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.in (reg_read));
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assign wait_out = fifo_wait;
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/*wait_in |
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fifo_wait |
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autotran |
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wait_pulse;
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*/
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assign dstaddr_out[AW-1:0] = srcaddr_in[AW-1:0];
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assign data_out[31:0] = read_data[31:0];
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assign srcaddr_out[31:0] = 32'b0;
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assign ctrlmode_out[4:0] = ctrlmode_in[4:0];
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assign ctrlmode_out[4:0] = datamode_in[4:0];
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emesh2packet e2p (.write_out (1'b1),
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/*AUTOINST*/
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// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.datamode_out (datamode_out[1:0]),
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.ctrlmode_out (ctrlmode_out[4:0]),
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.dstaddr_out (dstaddr_out[AW-1:0]),
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.data_out (data_out[AW-1:0]),
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.srcaddr_out (srcaddr_out[AW-1:0]));
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endmodule // spi_master_regs
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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