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oh/asiclib/hdl/asic_dffsq.v
aolofsson 289024fd89 Flattening directory tree (again)
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
2022-06-21 14:48:48 -04:00

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728 B
Verilog

//#############################################################################
//# Function: Positive edge-triggered static D-type flop-flop with async #
//# active low preset. #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module asic_dffsq #(parameter PROP = "DEFAULT") (
input d,
input clk,
input nset,
output reg q
);
always @ (posedge clk or negedge nset)
if(!nset)
q <= 1'b1;
else
q <= d;
endmodule