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oh/asiclib/hdl/asic_dsync.v
aolofsson 289024fd89 Flattening directory tree (again)
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
2022-06-21 14:48:48 -04:00

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972 B
Verilog

//#############################################################################
//# Function: Data Syncrhonizer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module asic_dsync #(parameter PROP = "DEFAULT") (
input clk, // clock
input nreset, // async active low reset
input in, // input data
output out // synchronized data
);
localparam SYNCPIPE=2;
reg [SYNCPIPE-1:0] sync_pipe;
always @ (posedge clk or negedge nreset)
if(!nreset)
sync_pipe[SYNCPIPE-1:0] <= 'b0;
else
sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-1:0],in};
assign out = sync_pipe[SYNCPIPE-1];
endmodule