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oh/asiclib/hdl/asic_header.v
aolofsson 289024fd89 Flattening directory tree (again)
- Creating an arbitrary 'src' directory really doesn't help much...
- Goal is to make each folder self contained
- Make meta repos and individual repos have the same directory structure
2022-06-21 14:48:48 -04:00

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735 B
Verilog

//#############################################################################
//# Function: Power supply header switch #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module asic_header #(parameter PROP = "DEFAULT") (
input sleep, // 1 = disabled vdd
input vddin, // input supply
output vddout // gated output supply
);
// Primitive Device
pmos m0 (vddout, vssin, sleep); //d,s,g
endmodule