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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
254 lines
9.6 KiB
Verilog
254 lines
9.6 KiB
Verilog
//#############################################################################
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//# Purpose: DMA registers #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see below) #
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//#############################################################################
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`include "edma_regmap.vh"
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module edma_regs (/*AUTOARG*/
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// Outputs
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reg_wait_out, reg_access_out, reg_packet_out, dma_en, mastermode,
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manualmode, datamode, ctrlmode, chainmode, irq, next_descr,
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curr_descr, stride_reg, count_reg, dstaddr_reg, srcaddr_reg,
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// Inputs
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clk, nreset, reg_access_in, reg_packet_in, reg_wait_in,
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fetch_access, fetch_packet, count, dstaddr, srcaddr, dma_state,
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update
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);
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// parameters
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parameter AW = 8; // address width
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parameter PW = 2*AW+40; // emesh packet width
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parameter DEF_CFG = 0; // default config after reset
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// clk, reset
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input clk; // main clock
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input nreset; // async active low reset
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// config interface
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input reg_access_in; // config register access
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input [PW-1:0] reg_packet_in; // config register packet
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output reg_wait_out; // pushback by register read
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output reg_access_out; // config readback
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output [PW-1:0] reg_packet_out; // config reacback packet
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input reg_wait_in; // pushback for readback
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// descriptor fetch interface
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input fetch_access; // fetch descriptor
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input [PW-1:0] fetch_packet; // fetch packet (mux with readback)
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// config outputs
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output dma_en; // enable dma
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output mastermode; // dma in master mode
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output manualmode; // 0=fetch descriptor, 1=assume config ready
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output [1:0] datamode; // transfer size (8,16,32,64 bits)
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output [4:0] ctrlmode; // ctrlmode
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output chainmode; // auto wrap around
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output irq; // interrupt output
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output [15:0] next_descr; // pointer to next descriptor
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output [15:0] curr_descr; // pointer to current descriptor
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// datapath regs
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output [31:0] stride_reg; // stride
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output [31:0] count_reg; // register transfer count
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output [63:0] dstaddr_reg; // register destination address
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output [63:0] srcaddr_reg; // register source address
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// datapath inputs
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input [31:0] count; // current count
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input [AW-1:0] dstaddr; // current destination address
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input [AW-1:0] srcaddr; // current source address
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// status
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input [3:0] dma_state; // dma sequencer state
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input update; // update registers
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//######################################################################
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//# BODY
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//######################################################################
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// regs
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reg [31:0] config_reg;
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reg [31:0] count_reg;
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reg [31:0] stride_reg;
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reg [63:0] dstaddr_reg;
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reg [63:0] srcaddr_reg;
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reg [31:0] status_reg;
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// wires
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wire reg_write;
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wire config_write;
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wire stride_write;
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wire count_write;
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wire srcaddr0_write;
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wire srcaddr1_write;
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wire dstaddr0_write;
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wire dstaddr1_write;
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wire status_write;
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wire irqmode;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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//################################
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//# DECODE
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//################################
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packet2emesh #(.AW(AW),
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.PW(PW))
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p2e (.packet_in (reg_packet_in[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]));
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assign reg_write = write_in & reg_access_in;
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assign config_write = reg_write & (dstaddr_in[6:2]==`EDMA_CONFIG);
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assign stride_write = reg_write & (dstaddr_in[6:2]==`EDMA_STRIDE);
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assign count_write = reg_write & (dstaddr_in[6:2]==`EDMA_COUNT);
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assign srcaddr0_write = reg_write & (dstaddr_in[6:2]==`EDMA_SRCADDR);
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assign srcaddr1_write = reg_write & (dstaddr_in[6:2]==`EDMA_SRCADDR64);
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assign dstaddr0_write = reg_write & (dstaddr_in[6:2]==`EDMA_DSTADDR);
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assign dstaddr1_write = reg_write & (dstaddr_in[6:2]==`EDMA_DSTADDR64);
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assign status_write = reg_write & (dstaddr_in[6:2]==`EDMA_STATUS);
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//################################
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//# CONFIG
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//################################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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config_reg[31:0] <= DEF_CFG;
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else if(config_write)
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config_reg[31:0] <= data_in[31:0];
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assign dma_en = config_reg[0]; // dma enabled
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assign mastermode = config_reg[1]; // dma in master mode
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assign chainmode = config_reg[2]; // autostart when done
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assign manualmode = ~config_reg[3]; // fetch descriptor if=1
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assign irqmode = config_reg[4]; // enable irq at end of transfer
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assign datamode[1:0] = config_reg[6:5]; // datamode (8/16/32/64 bits)
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assign ctrlmode[4:0] = 5'b0; // bits 10-11 reserved
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assign next_descr[15:0] = config_reg[31:16];// pointer to fetch descriptor
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//################################
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//# STRIDE
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//################################
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always @ (posedge clk)
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if(stride_write)
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stride_reg[31:0] <= data_in[31:0];
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//################################
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//# COUNT
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//################################
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always @ (posedge clk)
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if(count_write)
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count_reg[31:0] <= data_in[31:0];
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else if (update)
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count_reg[31:0] <= count[31:0];
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//################################
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//# SRCADDR
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//################################
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always @ (posedge clk)
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if(srcaddr0_write)
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srcaddr_reg[31:0] <= data_in[31:0];
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else if(srcaddr1_write)
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srcaddr_reg[63:32] <= data_in[31:0];
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else if (update)
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srcaddr_reg[AW-1:0] <= srcaddr[AW-1:0];
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//################################
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//# DSTADDR
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//################################
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always @ (posedge clk)
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if(dstaddr0_write)
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dstaddr_reg[31:0] <= data_in[31:0];
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else if(dstaddr1_write)
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dstaddr_reg[63:32] <= data_in[31:0];
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else if (update)
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dstaddr_reg[AW-1:0] <= dstaddr[AW-1:0];
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//################################
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//# STATUS
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//################################
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always @ (posedge clk)
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if(status_write)
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status_reg[31:0] <= data_in[31:0];
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else if (config_write)
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status_reg[31:0] <= {next_descr[15:0],
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12'b0,
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dma_state[3:0]};
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assign curr_descr[15:0] = status_reg[31:16];
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//################################
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//# READBACK CIRCUIT
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//################################
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//TODO: no readback for now
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assign reg_wait_out = 1'b0 ;
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assign reg_access_out = fetch_access;
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assign reg_packet_out[PW-1:0] = fetch_packet[PW-1:0];
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//################################
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//# READBACK CIRCUIT
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//################################
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assign irq = 1'b0;
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endmodule // edma_regs
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl")
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// End:
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///////////////////////////////////////////////////////////////////////////////
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// The MIT License (MIT) //
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// //
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// Copyright (c) 2015-2016, Adapteva, Inc. //
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// //
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// Permission is hereby granted, free of charge, to any person obtaining a //
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// copy of this software and associated documentation files (the "Software") //
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// to deal in the Software without restriction, including without limitation //
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// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
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// and/or sell copies of the Software, and to permit persons to whom the //
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// Software is furnished to do so, subject to the following conditions: //
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// //
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// The above copyright notice and this permission notice shall be included //
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// in all copies or substantial portions of the Software. //
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// //
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
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// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
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// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
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// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
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// //
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///////////////////////////////////////////////////////////////////////////////
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