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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
61 lines
1.9 KiB
Markdown
61 lines
1.9 KiB
Markdown
GPIO: General Purpose Software Programmable IO
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==============================================
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## Features
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* Input pins accessible through GPIO_IN register read
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* Output pins controllable through GPIO_OUT register writes
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* Vector wide "OR" interrupt on edge detection
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* Maskable input data and interrupts
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* Special And/or/xor register access modes for atomic control of output pins
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## Registers
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| Register Name |Addr[6:3]|Access |Default| Description |
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|---------------|---------|-------|-------|---------------------------------|
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| GPIO_DIR | 0x0 | WR | L | Direction(0=input, 1=output) |
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| GPIO_IN | 0x1 | RD | n/a | Input pin value |
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| GPIO_OUT | 0x2 | WR | L | Output pin value |
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| GPIO_OUTCLR | 0x3 | WR | n/a | Output = output & ~value |
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| GPIO_OUTSET | 0x4 | WR | n/a | Output = output "or" value |
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| GPIO_OUTXOR | 0x5 | WR | n/a | Output = output ^ value |
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| GPIO_IMASK | 0x6 | WR | H | Interrupt mask (1=mask) |
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| GPIO_ITYPE | 0x7 | WR | n/a | IRQ type (0=edge,1=level) |
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| GPIO_IPOL | 0x8 | WR | H | IRQ polarity (1=rising edge/high)|
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| GPIO_ILAT | 0x9 | RD | L | IRQ Status (1=latched irq) |
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| GPIO_ILATCLR | 0xA | WR | n/a | Clears ILAT(1=clear) |
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## Interface
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* clk
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* active low async reset
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* emesh register access interface
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* IO pin interface (in/out/tristate)
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## Parameters
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* AW : address space width (32/64)
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* N : number of IO (1-64)
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## Code
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* [gpio.v](hdl/gpio.v)
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* [gpio_regmap.vh](hdl/gpio_regmap.vh)
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## Building
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```cd
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cd $OH_HOME/gpio/dv
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./build.sh # build with Icarus
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./run.sh tests/test_regs.emf # run test
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gtkwave waveform.vcd # open waveform
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```
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## Language
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* Verilog
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## Authors
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* Andreas Olofsson
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## License
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* MIT
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