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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
210 lines
6.9 KiB
Verilog
210 lines
6.9 KiB
Verilog
//#############################################################################
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//# Purpose: SPI master Registers #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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`include "spi_regmap.vh"
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module spi_master_regs # (parameter CLKDIV = 1, // default clkdiv
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parameter AW = 32, // addresss width
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parameter PW = 104 // packet width
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)
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(
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//clk,reset, cfg
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input clk, // core clock
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input nreset, // async active low reset
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input hw_en, // block enable
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//io interface
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input [63:0] rx_data, // rx data
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input rx_access, // rx access pulse
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//control
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output cpol, // clk polarity (default is 0)
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output cpha, // clk phase shift (default is 0)
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output lsbfirst, // send lsbfirst
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output spi_en, // enable transmitter
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output manual_mode,// sets manual ss control
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output send_data, // controls ss in manual ss mode
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output reg [7:0] clkdiv_reg, // baud rate setting
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input [2:0] spi_state, // transmit state
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input fifo_prog_full, // fifo reached half/full
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input fifo_wait, // tx transfer wait
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//packet to transmit
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input access_in, // access from core
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input [PW-1:0] packet_in, // data to core
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output wait_out, // pushback from spi master
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//return packet
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output reg access_out, // writeback from spi
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output [PW-1:0] packet_out, // writeback data from spi
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input wait_in // pushback by core
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);
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//###############
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//# LOCAL WIRES
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//###############
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reg [7:0] config_reg;
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reg [7:0] status_reg;
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reg [63:0] rx_reg;
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reg [AW-1:0] reg_rdata;
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reg autotran;
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reg [AW-1:0] dstaddr_out;
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reg [4:0] ctrlmode_out;
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reg [1:0] datamode_out;
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wire [31:0] reg_wdata;
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wire reg_write;
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wire reg_read;
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wire config_write;
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wire status_write;
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wire clkdiv_write;
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wire cmd_write;
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wire tx_write;
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wire irq_en;
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wire wait_pulse;
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integer i;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] data_in; // From pe2 of packet2emesh.v
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wire [1:0] datamode_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From pe2 of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From pe2 of packet2emesh.v
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wire write_in; // From pe2 of packet2emesh.v
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// End of automatics
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//####################################
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//# DECODE
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//####################################
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packet2emesh #(.AW(AW),
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.PW(PW))
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pe2 (/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]),
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// Inputs
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.packet_in (packet_in[PW-1:0]));
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assign reg_write = access_in & write_in;
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assign reg_read = access_in & ~write_in;
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assign reg_wdata[31:0] = data_in[AW-1:0];
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assign config_write = reg_write & (dstaddr_in[5:0]==`SPI_CONFIG);
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assign status_write = reg_write & (dstaddr_in[5:0]==`SPI_STATUS);
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assign clkdiv_write = reg_write & (dstaddr_in[5:0]==`SPI_CLKDIV);
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assign cmd_write = reg_write & (dstaddr_in[5:0]==`SPI_CMD);
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assign tx_write = reg_write & (dstaddr_in[5:0]==`SPI_TX);
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//####################################
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//# CONFIG
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//####################################
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always @ (posedge clk or negedge nreset)
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if (~nreset)
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config_reg[7:0] <= 'b0;
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else if(config_write)
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config_reg[7:0] <= data_in[7:0];
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assign spi_en = hw_en & ~config_reg[0]; // disable spi (on by default)
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assign irq_en = config_reg[1]; // enable interrupt
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assign cpol = config_reg[2]; // cpol
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assign cpha = config_reg[3]; // cpha
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assign lsbfirst = config_reg[4]; // send lsb first
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assign manual_mode = config_reg[5]; // manual control of ss bit
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assign send_data = config_reg[6]; // ss bit
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//####################################
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//# STATUS
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//####################################
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always @ (posedge clk or negedge nreset)
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if (~nreset)
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status_reg[7:0] <= 'b0;
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else if(status_write)
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status_reg[7:0] <= reg_wdata[7:0];
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else
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status_reg[7:0] <= {5'b0, //7:4
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fifo_prog_full, //3
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1'b0, //reserved
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(rx_access | (~tx_write & status_reg[0]))};//0
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//####################################
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//# CLKDIV
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//####################################
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always @ (posedge clk or negedge nreset)
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if (~nreset)
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clkdiv_reg[7:0] <= CLKDIV;
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else if(clkdiv_write)
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clkdiv_reg[7:0] <= reg_wdata[7:0];
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//####################################
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//# RX REG
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//####################################
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always @ (posedge clk)
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if(rx_access)
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rx_reg[63:0] <= rx_data[63:0];
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//####################################
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//# READBACK
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//####################################
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//read back registers
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always @ (posedge clk)
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if(reg_read)
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case(dstaddr_in[4:0])
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`SPI_CONFIG : reg_rdata[31:0] <= {24'b0,config_reg[7:0]};
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`SPI_STATUS : reg_rdata[31:0] <= {24'b0,status_reg[7:0]};
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`SPI_CLKDIV : reg_rdata[31:0] <= {24'b0,clkdiv_reg[7:0]};
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`SPI_RX0 : reg_rdata[31:0] <= rx_reg[31:0];
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`SPI_RX1 : reg_rdata[31:0] <= rx_reg[63:32];
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default : reg_rdata[31:0] <= 32'hDEADBEEF;
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endcase // case (dstaddr_in[5:0])
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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access_out <= 1'b0;
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else
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access_out <= reg_read;
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always @ (posedge clk)
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begin
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dstaddr_out[AW-1:0] <= srcaddr_in[AW-1:0];
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ctrlmode_out[4:0] <= ctrlmode_in[4:0];
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datamode_out[1:0] <= datamode_in[1:0];
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end
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//create a single cycle pulse on register read
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oh_edge2pulse e2pulse (.out (wait_pulse),
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.nreset (nreset),
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.clk (clk),
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.in (reg_read));
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//TODO: fix!
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assign wait_out = fifo_wait;
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emesh2packet #(.AW(AW),
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.PW(PW))
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e2p (.write_out (1'b1),
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.srcaddr_out ({(AW){1'b0}}),
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.data_out (reg_rdata[AW-1:0]),
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/*AUTOINST*/
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// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.datamode_out (datamode_out[1:0]),
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.ctrlmode_out (ctrlmode_out[4:0]),
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.dstaddr_out (dstaddr_out[AW-1:0]));
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endmodule // spi_master_regs
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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