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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
module testbench();
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localparam N = 32;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire clk1; // From oh_simctrl of oh_simctrl.v
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wire clk2; // From oh_simctrl of oh_simctrl.v
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wire nreset; // From oh_simctrl of oh_simctrl.v
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wire out; // From oh_pulse of oh_pulse.v
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wire start; // From oh_simctrl of oh_simctrl.v
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wire vdd; // From oh_simctrl of oh_simctrl.v
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wire vss; // From oh_simctrl of oh_simctrl.v
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// End of automatics
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oh_pulse #(.N(N))
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oh_pulse(.en (1'b1),
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.clk (clk1),
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.mask (32'h0000000f),
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/*AUTOINST*/
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// Outputs
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.out (out),
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// Inputs
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.nreset (nreset));
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oh_simctrl oh_simctrl(//TODO: implement
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.stim_done (1'b0),
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.test_done (1'b0),
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.test_diff (1'b0),
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.dut_active (1'b1),
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/*AUTOINST*/
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// Outputs
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.nreset (nreset),
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.clk1 (clk1),
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.clk2 (clk2),
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.start (start),
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.vdd (vdd),
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.vss (vss));
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endmodule // tb
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// Local Variables:
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// verilog-library-directories:("." "../hdl")
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// End:
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