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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
33 lines
685 B
Verilog
33 lines
685 B
Verilog
/*###########################################################################
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*#An I/O clock buffer
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*###########################################################################
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*
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* BUIOs can drive:
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* -a single I/O clock network in the same region/bank
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*
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* BUIOs can be driven by:
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* -SRCCs and MRCCs in the same clock region
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* -MRCCs in an adjacent clock region using BUFMRs
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* -MMCMs clock outputs 0-3 driving the HPC in the same clock region
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*
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*
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* Input to Output Delay (Zynq7010/7020): 1.61/1.32/1.16 (-1/-2/-3 grade)
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*
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*
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*/
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module BUFIO (/*AUTOARG*/
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// Outputs
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O,
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// Inputs
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I
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);
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output O;
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input I;
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assign O=I;
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endmodule
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